Semiconductor device and method of manufacturing the same
AssigneeOki Electric Industry Co., Ltd.
InventorToshiyuki Nakamura
Life of this patent
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Abstract
The present invention aims to provide a field effect transistor which inhibits an aggregation of silicon atoms attendant on heat treatment and has stable source/drain shapes. The field effect transistor according to the present invention is manufactured using a substrate on which a silicon layer, an buried oxide film (BOX film) and an SOI layer are stacked in order. The field effect transistor has an element isolation layer formed in the SOI layer and further includes visored portions provided so as to cover angular portions on the main surface side of an activation layer defined by the element isolation layer.
Claims22
A field effect transistor, comprising:
- a first semiconductor layer;
- a first insulating layer formed over said first semiconductor layer;
- a second semiconductor layer formed over said first insulating layer;
- an element isolation layer formed in said second semiconductor layer;
- and
- a second insulating layer formed so as to cover each of angular portions on the main surface side of an activation layer defined by said element isolation layer.
A field effect transistor, comprising:
- a first semiconductor layer;
- a first insulating film formed over said first semiconductor layer;
- a second semiconductor layer formed over said first insulating film;
- an element isolation region formed within said second semiconductor layer;
- and
- a second insulating film formed so as to cover each of ends on the main surface side of an activation region defined by said element isolation region.
A field effect transistor, comprising:
- a first semiconductor layer;
- a first insulating layer formed over said first semiconductor layer;
- a second semiconductor layer formed over said first insulating layer;
- and
- an element isolation layer formed within said second semiconductor layer, and
- wherein said element isolation layer has visored portions for covering angular portions on the main surface side of an activation layer defined by said element isolation layer.
A field effect transistor, comprising:
- a first semiconductor layer;
- a first insulating film formed over said first semiconductor layer;
- a second semiconductor layer formed over said first insulating film;
- and
- an element isolation region formed within said second semiconductor layer, and
- wherein said element isolation region has visored portions for covering ends of an activation region defined by said element isolation region.
A method of manufacturing a field effect transistor, comprising the following steps:
- preparing a substrate on which a first semiconductor layer, a first insulating layer and a second semiconductor layer are stacked in order;
- forming an element isolation layer within the second semiconductor layer;
- forming a gate electrode over the substrate with a gate insulating film interposed therebetween;
- forming a second insulating layer so as to cover each of angular portions on the main surface side of an activation layer defined by the element isolation layer;
- and
- forming a third semiconductor layer by a selective epitaxial growth method with said gate electrode and said second insulating film as masks.
A method of manufacturing a field effect transistor, comprising the following steps:
- preparing a substrate on which a first semiconductor layer, a first insulating layer and a second semiconductor layer are stacked in order;
- forming an element isolation region within the second semiconductor layer;
- forming a gate electrode over the substrate with a gate insulating film interposed therebetween;
- forming a second insulating layer so as to cover each of ends of an activation region defined by the element isolation region;
- and
- forming a third semiconductor layer by a selective epitaxial growth method with said gate electrode and said second insulating film as masks.
Dependencies are inferred from the claim text.