Flash memory including means of checking memory cell threshold voltages
AssigneeSTMicroelectronics S.r.l.
InventorsPaola Cavaleri, Bruno Leconte, Sebastien Zink, Jean Devin
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Abstract
A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a threshold voltage less than a given threshold are reprogrammed. The checking circuit includes a non-volatile counter formed by at least one row of floating gate transistors, a reading circuit for reading the address of a page to be checked in the counter, and an incrementing circuit for incrementing the counter after a page has been checked.
Claims20
Process for recording data in a FLASH memory (MEM1) including a step in which a memory page (Pi) is erased and reprogrammed, and a step in which the threshold voltage of programmed transistors is checked and programmed transistors with a threshold voltage less than a determined threshold (VVRFY) are reprogrammed if necessary,
- characterized in that the checking step, including reprogramming if necessary, is applied to floating gate transistors on at least one page, the address of which is read in a non-volatile counter (CMPT) formed by at least one row of floating gate transistors.
FLASH memory (MEM1) erasable by page, including:
- a memory array (FMA) including a plurality of floating gate transistors connected through their gates to word lines (WLi), the transistors connected to the same word line forming a page (Pi) in the memory array, and a set of pages forming a sector (S1-S8) in the memory array,
- means of checking the threshold voltage of floating gate transistors and reprogramming the programmed transistors with a threshold voltage less than a given threshold (VVRFY),
- characterized in that the check means comprise:
- a non-volatile counter (CMPT) formed by at least one row of floating gate transistors,
- means (SREG, CONVC, DETZ) of reading the address of at least one page to be checked in the counter, and
- means (SREG, LT) of incrementing the counter after checking at least one page.
Dependencies are inferred from the claim text.