Method of fabricating a dram transistor with a dual gate oxide technique

A process for creating two thicknesses of gate oxide within a memory device constructed on a substrate on which a local oxidation of silicon process has been performed, comprising the steps of:

• masking a pad oxide with a photoresist to protect the area where the memory array will be formed;
• stripping the pad oxide not protected by the photoresist;
• stripping the photoresist;
• and
• growing a gate oxide layer which is thinner than the pad oxide layer.

A process for creating two thicknesses of gate oxide within a memory device, comprising the steps of:

• growing a first oxide layer on the upper surface of a substrate;
• depositing a silicon nitride layer on top of the first oxide layer;
• patterning the silicon nitride layer with a photoresist mask to define field oxide areas;
• stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer;
• removing the remnants of the silicon nitride layer;
• stripping the pad oxide layer and growing a sacrificial oxide layer;
• masking the sacrificial oxide layer with a photoresist to protect the area where the memory array will be formed;
• stripping the sacrificial oxide not protected by the photoresist;
• stripping the photoresist;
• and
• growing a gate oxide layer which is thinner than the sacrificial oxide layer.

A process for creating two thicknesses of gate oxide within a memory device constructed on a substrate, comprising the steps of:

• growing a first oxide layer on the upper surface of a substrate;
• depositing a silicon nitride layer on top of the first oxide layer;
• patterning the silicon nitride layer with a photoresist mask to define field oxide areas;
• stripping the oxide layer and regrowing a pad oxide layer on the upper surfaces of the substrate not covered by the remnants of the silicon nitride layer;
• removing the remnants of the silicon nitride layer;
• masking the pad oxide layer with a photoresist to protect the area where the memory array will be formed;
• stripping the pad oxide not protected by the photoresist;
• stripping the photoresist;
• and
• growing a gate oxide layer which is thinner than the pad oxide layer.