Method of fabricating a high-voltage transistor

A method of fabricating an extended drain of a high-voltage field-effect transistor (HVFET) comprising:

• forming a well region of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, the well region having a laterally extended portion with a lateral boundary;
• successively implanting a first dopant of the second conductivity type in the well region, each implant being performed at a different energy through the first surface to form a first plurality of buried layers within the laterally extended portion of the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the first conductivity type is formed within the first substrate;
• bonding the first surface of the first substrate to a second substrate of the second conductivity type;
• thinning the first substrate from the second surface;
• successively implanting a second dopant of the second conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended portion of the well region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed within the first substrate.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• successively implanting a first dopant of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region and a second plurality of buried layers in a source region of the first substrate, each of the first and second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region, a section of the source region being partially masked at the first surface such that the second plurality of buried layers in the source region is formed into a first continuous doped region;
• bonding the first surface of the first substrate to a second substrate of the first conductivity type;
• thinning the first substrate from the second surface;
• successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a third plurality of buried layers within the laterally extended region and a fourth plurality of buried layers in the source region of the first substrate, each of the third and fourth plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region, the section of the source region being partially masked at the second surface such that the fourth plurality of buried layers in the source region is formed into a second continuous doped region, wherein the first and second continuous doped regions are connected to form a single continuous doped region that extends to the second substrate;
• forming a gate insulated from the first substrate by a gate oxide layer, the gate extending over the second surface adjacent the laterally extended region of the first substrate;
• forming a body region of the first conductivity type connected to the single continuous doped region in the first substrate, the body region adjoining the second surface and having a lateral boundary that extends beneath the gate;
• forming a source diffusion region of the second conductivity type in the body region spaced-apart from the lateral boundary, a channel region being formed in the body region between the source diffusion region and the lateral boundary;
• and
• forming a drain diffusion region of the second conductivity type in the first substrate at a side of the laterally extended region opposite the source diffusion region.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• successively implanting a first dopant of the first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region of the first substrate, each of the first plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;
• bonding the first surface of the first substrate to a second substrate of the first conductivity type;
• thinning the first substrate from the second surface;
• successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended region, each of second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;
• forming a gate insulated from the first substrate by a gate oxide layer, the gate extending over the second surface adjacent the laterally extended region of the first substrate;
• forming a body region of the first conductivity type in the first substrate, the body region adjoining the second surface and having a lateral boundary that extends beneath the gate;
• forming a source diffusion region of the second conductivity type in the body region spaced-apart from the lateral boundary, a channel region being formed in the body region between the source diffusion region and the lateral boundary;
• and
• forming a drain diffusion region of the first conductivity type in the first substrate on a side of the laterally extended region opposite the source diffusion region.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• successively implanting a first dopant of the first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, each implant being performed at a different energy through the first surface to form a first plurality of buried layers in a laterally extended region of the first substrate, each of the first plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;
• bonding the first surface of the first substrate to a second substrate of the first conductivity type;
• thinning the first substrate from the second surface;
• successively implanting a second dopant of the first conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended region, each of second plurality of buried layers being disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed in the laterally extended region;
• forming a trench gate insulated from the first substrate by a gate oxide layer that extends vertically from the second surface of the first substrate adjacent one side of the laterally extended region;
• forming a body region of the first conductivity type in the first substrate, the body region adjoining the second surface and the gate oxide;
• forming a source diffusion region of the second conductivity type in the body region adjacent the gate oxide, a vertical channel region being formed in the body region between the source diffusion region and the first substrate near the gate oxide;
• and
• forming a drain diffusion region of the first conductivity type in the first substrate on a side of the laterally extended region opposite the source diffusion region.

A method of fabricating a high-voltage field-effect transistor (HVFET) comprising:

• forming a well region of a first conductivity type in a first substrate of a second conductivity type, the first substrate having first and second opposing surfaces, the well region having a laterally extended portion with a lateral boundary;
• successively implanting a first dopant of the second conductivity type in the well region, each implant being performed at a different energy through the first surface to form a first plurality of buried layers within the laterally extended portion of the well region, each of the first plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the first surface such that a corresponding first plurality of JFET conduction channels of the first conductivity type is formed within the first substrate;
• bonding the first surface of the first substrate to a second substrate of the second conductivity type;
• thinning the first substrate from the second surface;
• successively implanting a second dopant of the second conductivity type in the first substrate, each implant being performed at a different energy through the second surface so as to form a second plurality of buried layers within the laterally extended portion of the well region, each of the second plurality of buried layers being of the second conductivity type and disposed at a different vertical depth in the first substrate relative to the second surface such that a corresponding second plurality of JFET conduction channels of the second conductivity type is formed within the first substrate;
• forming a gate insulated from the substrate by a gate oxide layer, the gate extending over the second surface of the first substrate adjacent the laterally extended portion of the well region;
• forming a body region of the second conductivity type in the first substrate, the body region adjoining the second surface and extending across the lateral boundary into the well region beneath the gate;
• implanting a dopant of the first conductivity type in the body region to form a source diffusion region spaced-apart from the well region, and also into the well region to form a drain diffusion region, a channel region being formed in the body region between the source diffusion region and the well region under the gate;
• and
• forming source and drain electrodes connected to the source and drain diffusion regions, respectively.