US 2002/0118894 A1Published application

Image processor

AssigneeMega Chips Corporation

InventorsKazuya Morimoto, Takashi Matsutani, Gen Sasaki

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Abstract

Image dividing means of an RPU divides raw image data into divided image data A1 having 2048 horizontal pixels and A2 having 1024 horizontal pixels. The divided image data A1 is continuously processed in single pixel processing means and multiple pixel processing means and thereafter transferred to and stored in a buffer. The divided image data A2 is processed in the single pixel processing means and thereafter transferred to and temporarily stored in another buffer. The multiple pixel processing means reads and processes divided image data A2a stored in this buffer and thereafter transfers and stores the same to and in still another buffer. Image combining means reads divided image data A1b and A2b stored in the buffers and combines the same with each other. Thus, an image processing time and a cost can be reduced even if raw image data having horizontal pixels in a number exceeding the capacity of a line memory is received.

Claims7

Dependent claims

An image processor comprising an image processing circuit image-processing image data input therein and a main memory receiving and temporarily storing transferred said data processed in said image processing circuit, wherein

said image processing circuit has a temporary storage area temporarily storing pixel data of a plurality of lines of said image data, image dividing means dividing said image data into divided image data storable in said temporary storage area, single pixel processing means executing image processing on said divided image data in units of single pixels and multiple pixel processing means executing image processing in units of multiple pixels after said temporary storage area stores said divided image data processed in said single pixel processing means, and
said main memory has a first buffer area storing first divided image data continuously processed in said single pixel processing means and said multiple pixel processing means among said divided image data, a second buffer area storing second divided image data processed in said single pixel processing means among said divided image data and a third buffer area storing data obtained by processing said second divided image data read from said second buffer area in said multiple pixel processing means,
said image processor further comprising image combining means combining said first divided image data stored in said first buffer area and said data stored in said third buffer area with each other.

An image processor comprising an image processing circuit image-processing image data input therein, a main memory receiving and temporarily storing transferred said data processed in said image processing circuit and a DMA controller controlling data transfer between said main memory and said image processing circuit, wherein

said image processing circuit has a temporary storage area temporarily storing pixel data of a plurality of lines of said raw image data, image dividing means dividing said image data into divided image data storable in said temporary storage area, single pixel processing means executing image processing on said divided image data in units of single pixels and multiple pixel processing means executing image processing in units of multiple pixels after said temporary storage area stores said divided image data processed in said single pixel processing means,
said main memory has a first buffer area storing first divided image data continuously processed in said single pixel processing means and said multiple pixel processing means among said divided image data and a second buffer area storing second divided image data processed in said single pixel processing means among said divided image data,
said first buffer area also stores data obtained by processing said second divided image data read from said second buffer area in said multiple pixel processing means, and
said DMA controller makes addressing when transferring said first and second divided image data to said first buffer area thereby combining the same into a single image and storing said single image.

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Dependencies are inferred from the claim text.