Loading patent…
AssigneeNokia Corporation
InventorsThorsten Schier, Jonas Askeroth, Greger Sjoberg
Estimating the term…
A digital and a multiplication method are described, which lead to an efficient architecture for hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.
A digital filter comprising:
A digital filter according to anyone of the preceding claims, wherein said other weighted sample data correspond to input sample data the value of which can be obtained by multiplying another input sample data by a factor equal to two or a power of two, and are generated by using a corresponding one of said pre-stored weighted sample data relating to said other input sample data and performing a corresponding bit shifting operation in accordance with said multiplication factor.
A digital filter according to anyone of the preceding claims, wherein said look-up table means (2) comprises ROM tables for storing said pre-stored weighted sample data.
A digital filter according to anyone of the preceding claims, wherein said digital filter is implemented as an FPGA.
A method for performing digital filtering of input sample data, comprising the steps of:
A method for performing a multiplication based on a look-up table, comprising the steps of:
Dependencies are inferred from the claim text.