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US 2002/0118708 A1Published application
Multi-stage multiplexer
AssigneeIntel Corporation
InventorsVenkat S. Veeramachaneni, Dinesh Somasekhar
Life of this patent
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Abstract
A multiplexer includes a first stage that has tri-state buffers each of which has split outputs and a final stage that has a tri-state buffer with an output. The multiplexer includes circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.
Claims30
A multiplexer comprising:
- a first stage including tri-state buffers, each of which has split outputs;
- a final stage including a tri-state buffer having an output;
- and
- circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.
1 more element
A multiplexer comprising:
- stages including a first stage, at least one intermediate stage, and a final stage having an input,
- the first stage and the at least one intermediate stage including tri-state buffers each of which has a pair of segregated outputs coupled to a subsequent stage, and
- control circuitry to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.
An apparatus comprising:
- an arithmetic logic unit including an adder, a programmable logic unit,
- a static multiplexer arranged to receive data signals from the adder and the programmable logic unit;
- and
- a bus coupled to an output of the multiplexer, the multiplexer including:
- a first stage including tri-state buffers each of which has split outputs;
- a final stage including a tri-state buffer having an output;
- and
- circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.
5 more elements
An apparatus comprising:
- an arithmetic logic unit including an adder and a programmable logic unit,
- a static multiplexer arranged to receive data signals from the adder and the programmable logic unit;
- a bus coupled to an output of the multiplexer;
- the multiplexer including stages including a first stage, an intermediate stage, and a final stage including an output,
- the first stage and the intermediate stage including tri-state buffers each of which has a pair of segregated outputs coupled to a subsequent stage, and
- control circuitry configured to enable or disable a signal at an input of a selected one of the first-stage buffers to propagate to the output of the final-stage buffer.
3 more elements
A method comprising:
- causing a signal at an input to a selected one of a plurality of tri-state buffers to be passed to a particular one of a pair of split outputs associated with the selected buffer;
- and
- receiving the signal from the particular split output in a first subsequent tri-state buffer.
A method comprising:
- receiving signals representing results of arithmetic and logical operations;
- and
- causing a selected one of the signals to pass through a plurality of cascaded tri-state buffers each of which has split outputs.
Dependencies are inferred from the claim text.