Acquisition aid circuit

A method of presetting a phase locked loop to a lock range of a bitstream receiver clock with a network bitstream, the method comprising:

• generating a beat frequency from a reference clock and a bitstream receiver clock, wherein the reference clock has a reference clock frequency and the bitstream receiver clock has a receiver frequency;
• based on the beat frequency, determining if the receiver clock frequency varies by more than a first predetermined amount from a frequency associated with the bitstream;
• temporarily locking the receiver frequency to the reference clock frequency at least partly in response to determining that the receiver clock frequency varies by more than the first predetermined amount;
• and
• synchronizing the receiver clock frequency to the bitstream at least partly in response to determining that the receiver clock frequency does not vary by more than the first predetermined amount.

A method of preparing a VCO clock for synchronization with a bitstream, comprising:

• receiving a reference clock signal having a first frequency and the VCO clock signal having a second frequency, the VCO clock signal intended to be synchronized with a serial data stream;
• generating a beat frequency related to a difference between the first frequency and the second frequency;
• measuring an interval between at least a first beat and a second beat;
• determining if the interval exceeds a first predetermined amount;
• and
• if the interval fails to exceed the first predetermined amount, which indicates that the first frequency and the second frequency are not sufficiently matched, synchronizing the VCO clock signal with the reference clock signal.

A synchronization acquisition circuit, comprising:

• a first clock terminal configured to receive a first clock signal;
• a second clock terminal configured to receive a second clock signal;
• a differentiator circuit coupled to the first and the second clock terminals, the differentiator circuit configured to generate a beat signal having a beat frequency based on the first and second clock signals;
• a beat interval circuit coupled to the differentiator circuit, the beat interval circuit configured to determine when a beat interval range of the beat signal exceeds a predetermined threshold, the beat interval circuit further configured to generate a signal that causes the first clock to be synchronized with the second clock when the threshold is not exceeded within a first period of time.