Method and system for frame and pointer alignment of SONET data channels

A system for processing digital signals comprising:

• a first adder circuit comprising:
• a first pointer follower to receive a first digital signal having a first signal frame, a first embedded payload and a first pointer follower (“PF”) pointer, extract said first embedded payload from said first digital signal and forward said first embedded payload;
• a first elastic buffer in electrical connection with said first pointer follower operable to receive, delay and forward said first embedded payload;
• a first pointer generator to receive said first embedded payload and a synchronization pulse and construct a first new digital signal comprising said first embedded payload, a first new signal frame and a first pointer generator (“PG”) pointer, wherein the location of said first new signal frame in said first new digital signal is determined according to said synchronization pulse;
• and
• a second adder circuit comprising:
• a second pointer follower to receive a second digital signal having a second signal frame, a second embedded payload and a second pointer follower pointer (“PF pointer”), extract said second embedded payload from said second digital signal and forward said second embedded payload;
• a second elastic buffer in electrical connection with said second pointer follower operable to receive, delay and forward said second embedded payload;
• and
• a second pointer generator to receive said second embedded payload and construct a second new digital signal comprising said second embedded payload, a second new signal frame and a second PG pointer, wherein the location of said second new signal frame within said second new digital signal is determined by said synchronization pulse and wherein said second new signal frame is aligned with said first new signal frame;
• and
• a synchronization module to generate said synchronization pulse according to a predefined schedule and operable to communicate said synchronization pulse to said first adder circuit and to said second adder circuit.

A method for processing digital signals comprising:

• receiving a first digital signal at a first pointer follower (“PF”), having a first signal frame, a first embedded payload and a first PF pointer;
• extracting said first embedded payload from said first digital signal;
• forwarding said first embedded payload;
• delaying said first embedded payload at a first elastic buffer and forwarding said first embedded payload to first pointer generator;
• constructing a first new digital signal comprising said first embedded payload, a first new signal frame and a first pointer generator (“PG”) pointer at said first pointer generator, wherein the location of said first new signal frame within said first new digital signal is determined according to a synchronization pulse;
• and
• receiving a second digital signal at a second pointer follower having a second signal frame, a second embedded payload and a second PF pointer, extracting said second embedded payload from said second digital signal;
• forwarding said second embedded payload;
• delaying said second embedded payload at a second elastic buffer and forwarding said second embedded payload to a second pointer generator;
• and
• constructing a second new digital signal comprising said second embedded payload, a second new signal frame and a second PG pointer at said second pointer generator, wherein the location of said second new signal frame is determined according to said synchronization pulse;
• and
• generating said synchronization pulse according to a predefined schedule and communicating said synchronization pulse to said first pointer generator and said second pointer generator.

A system for processing a digital signal, comprising:

• a pointer follower to receive a first digital signal having a first signal frame, a first embedded payload and a pointer follower (“PF”) pointer, extract said first embedded payload from said first digital signal and forward said first embedded payload;
• an elastic buffer in electrical connection with said pointer follower operable to receive, delay and forward said first embedded payload;
• p1 a pointer generator to receive said first embedded payload and a synchronization pulse and construct a new digital signal comprising said first embedded payload, a new signal frame, and a pointer generator (“PG”) pointer, wherein the location of said new signal frame within said new digital signal is determined according to said synchronization pulse;
• a synchronization module to generate said synchronization pulse according to a predetermined schedule and communicate said synchronization pulse to said pointer generator;
• a first comparator operable to compare the value of said PF pointer and the value of said PG pointer and generate a pointer offset signal;
• and
• a second comparator operable to compare said pointer offset signal to a target offset signal, generate an increment/decrement request signal based on the comparison, and communicate the increment/decrement request signal to said elastic buffer;
• and
• wherein said elastic buffer delays said embedded payload according to said increment/decrement signal.