Semiconductor memory device and method for reading information of therefrom

A semiconductor memory device comprising:

• a plurality of memory cells for storing first cell information or second cell information, wherein the first cell information is associated with logic level “0” and the second cell information is associated with logic level “1”;
• a plurality of word lines connected to the memory cells for supplying the memory cells with word line voltage;
• a plurality of bit lines connected to the memory cells for conveying charge corresponding to the first or second cell information from one of the memory cells;
• a plurality of dummy cells respectively connected to the bit lines for supplying an associated one of the bit lines with complementary charge;
• and
• a plurality of dummy word lines respectively connected to the dummy cells for supplying the associated the dummy cells with dummy word line voltage, wherein the first cell information is read based on the charge conveyed to the bit line associated with the memory cell connected to an activated one of the word lines and wherein the second cell information is read based on the complementary charge supplied to the bit line associated with the dummy cell connected to an activated one of the dummy word lines.

A method for reading cell information from a semiconductor memory device, wherein the semiconductor memory device includes a plurality of memory cells for holding charge corresponding to first cell information or second cell information, a plurality of pairs of bit lines connected to the memory cells, each pair of bit lines including a bit line and an inverting bit line, the first cell information being associated with logic level “0” and the second cell information being associated with logic level “1”, a plurality of word lines connected to the memory cells for supplying the memory cells with word line voltage, a plurality of bit lines connected to the memory cells for receiving charge corresponding to the first or second cell information from one of the memory cells, a plurality of dummy cells respectively connected to the pairs of bit lines for supplying an associated one of the pair of bit lines with complementary charge, a plurality of dummy word lines respectively connected to the dummy cells for supplying the associated one of the dummy cells with dummy word line voltage, and a plurality of sense amplifiers respectively connected to the pairs of bit lines for amplifying the voltage between the associated one of the pairs of bit lines, the method comprising:

• a first step for activating at least one of the word lines;
• a second step for providing the first cell information to the bit line associated with the memory cell connected to the activated one of the word lines from the memory cell;
• a third step for activating at least one of the dummy word lines;
• a fourth step for supplying the complementary charge to the bit line associated with the dummy cell connected to the activated one of the dummy word lines from the connected dummy cell;
• and
• a fifth step for activating the sense amplifier connected to the bit line supplied with the complementary charge before the second cell information is read to the bit line.

A method for reading cell information from a semiconductor memory device, wherein the semiconductor memory device includes a plurality of memory cells for holding charge corresponding to first cell information or second cell information, a plurality of pairs of bit lines connected to the memory cells, each pair of bit lines including a bit line and an inverting bit line, the first cell information being associated with logic level “0” and the second cell information being associated with logic level “1”, a plurality of word lines connected to the memory cells for supplying the memory cells with word line voltage, a plurality of bit lines connected to the memory cells for receiving charge corresponding to the first or second cell information from one of the memory cells, a plurality of dummy cells respectively connected to the pairs of bit lines for supplying an associated one of the pair of bit lines with complementary charge, a plurality of dummy word lines respectively connected to the dummy cells for supplying the associated one of the dummy cells with dummy word line voltage, and a plurality of sense amplifiers respectively connected to the pairs of bit lines for amplifying the voltage between the associated one of the pairs of bit lines, and wherein the semiconductor memory device has a cell transistor threshold value voltage of each of the memory cells, a precharge voltage, a first sum voltage of the threshold value voltage and the precharge voltage, a write voltage for writing the second information to the memory cell, and a second sum voltage of the write voltage and the threshold value voltage, the method comprising:

• a first step for increasing voltage of at least one of the word lines from a reference voltage to a value greater than or equal to the threshold value voltage and less than the first sum voltage;
• a second step for providing the charge corresponding to the first cell information to the bit line associated with the memory cell connected to the at least one of the word lines;
• a third step for activating at least one of the dummy word lines;
• a fourth step for supplying the complementary charge to the bit line associated with the dummy cell connected to the activated one of the dummy word lines from the connected dummy cell;
• a fifth step for activating the sense amplifier connected to the bit line supplied with the complementary charge before the second cell information is read to the connected bit line from the memory cell;
• and
• a sixth step for increasing voltage at the at least one of the word lines to a value that is greater than or equal to the second sum voltage.