Memory circuit redundancy control

A memory having flexible column stick redundancy, comprising:

• a plurality of interconnected memories, each memory having a multi-column stick configuration, each column stick comprising a plurality of data lines;
• a first redundant column stick associated with each memory, each column stick comprising a plurality of data lines;
• a second redundant column stick associated with each memory, each column stick comprising a plurality of data lines;
• a redundancy control associated with each memory and identifying a faulty operating column stick in the associated memory and generating a shift control signal for the associated memory;
• and
• a shift multiplexer associated with each memory and responsive to the shift control signal to substitute in the associated memory either the first redundant column stick or the second redundant column stick for an identified faulty operating column stick in the associated memory.

A memory having flexible row stick redundancy, comprising:

• a memory having a multi-row stick configuration, each row comprising a plurality of data rows;
• a plurality of redundant row sticks each comprising a plurality of data rows;
• a redundancy control identifying a faulty operating row stick in the memory and generating a shift control signal;
• and
• a shift multiplexer responsive to the shift control signal to substitute in the memory a redundant row stick for the identified faulty operating row stick.

A memory having flexible column stick and row stick redundancy, comprising:

• a memory having a multi-column stick and multi-row stick configuration, each column stick and each row stick comprising a plurality of data lines;
• a first redundant column stick comprising a plurality of data lines;
• a second redundant column stick comprising a plurality of data lines;
• a first redundant row stick comprising a plurality of data rows;
• a second redundant row stick comprising a plurality of data lines;
• a column redundancy control identifying a faulty operating column stick in the memory and generating a column shift control signal;
• a column shift multiplexer responsive to the column shift control signal to substitute in the memory either the first redundant column stick or the second redundant column stick for an identified faulty operating column stick in the memory;
• a row redundancy control identifying a faulty operating row stick in the memory and generating a row shift control signal;
• and
• a row shift multiplexer responsive to the row shift control signal to substitute in the memory either the first redundant row stick or the second redundant row stick for an identified faulty operating row stick in the memory.