Method of programming non-volatile semiconductor memory device

A method of programming a non-volatile semiconductor memory device including a semiconductor substrate of a first conductive type;

• a first well area of a second conductive type formed in the semiconductor substrate of the first conductive type;
• a second well area of the first conductively type formed in the first well area;
• a memory cell array composed of a plurality strings, the memory cell array being formed in the second well area, wherein each of the strings is made of a first select transistor having a drain coupled to a corresponding bitline, a second select transistor having a source coupled to a common source line, and a plurality of memory cells serially connected between a source of the first select transistor and a drain of the second select transistor;
• a first select line commonly connected to first select transistors of the strings;
• a second select line commonly connected to second select transistors of the strings;
• a plurality of wordlines each being coupled to memory cells of the respective strings, wherein adjoining memory cells coupled to the same wordline are electrically isolated from each other by a field area, wherein, along the same wordline, the adjoining memory cells, and the field area comprises a parasitic MOS transistor, wherein the same wordline acts as a gate of the parasitic MOS transistor, wherein one channel of the adjoining memory cells acts as a drain of the parasitic MOS transistor, and the other channel acts as a source of the parasitic MOS transistor, and wherein the second well area adjacent to the field area between the adjoining memory cells acts as a channel of the MOS transistor;
• and page buffers for temporarily storing data bits to be programmed in the memory cell array, the method comprising the steps of:
• (a) supplying one of first and second supply voltages respectively to the bitlines, with the second well area biased with the first supply voltage, and the common source line biased with the second supply voltage higher than the first supply voltage;
• (b) cutting off the first supply voltage applied to the second well area in order to make the second well area achieve a floating state;
• (c) lowering the voltage applied to the common source line from the second supply voltage to a coupling induction voltage in order to bias the second well area with a coupling voltage lower than the first supply voltage through a coupling capacitance between the second well area and the common source line;
• and
• (d) supplying a program voltage to one of the plurality of wordlines while the floating second well area is biased with the coupling voltage.

In a non-volatile memory device including an array of memory cells formed in a pocket well of a semiconductor substrate, a method of programming the memory cells, comprising:

• directly biasing the pocket well with a first biasing voltage;
• removing the first biasing voltage to the pocket well and allowing the pocket well to float;
• indirectly biasing the floating pocket well;
• and
• applying a programming voltage to one or more of the memory cells during a time period in which the pocket well is indirectly biased.

In a memory device including an array of non-volatile memory cells formed in a pocket well of a semiconductor substrate, a method of programming the memory cells, comprising:

• biasing the pocket well with a first biasing voltage;
• removing the first biasing voltage to the pocket well and allowing the pocket well to float;
• biasing the floating pocket well with a coupling voltage;
• and
• programming one or more of the memory cells after the first biasing voltage has been removed from the pocket well.