High speed data capture circuit for a digital device

An integrated memory circuit comprising:

• at least one data terminal for using an externally applied data signal for storage in a storage array of said memory circuit;
• a clock terminal for receiving an externally applied clock signal;
• at least one latch for latching in data received at said at least one data terminal in accordance with a clock signal received at said terminal and having an output for providing a data signal to said storage array;
• at least one first conductive path connecting said at least one data terminal to said latch;
• and
• at least one second conductive path connecting said clock terminal to said at least one latch;
• said at least one first and second conductive paths being approximately equal in length.

A processing system comprising:

• a processor for processing data;
• and
• a memory device coupled to said processor;
• at least one of said processor and memory device comprising a data capture circuit, said data capture circuit comprising:
• at least one data terminal for receiving an externally applied data signal;
• a clock terminal for receiving an externally applied clock signal;
• at least one latch for latching in data received at said at least one data terminal in accordance with a clock signal received at said clock terminal;
• at least one first conductive path connecting said at least one data terminal to said latch;
• and
• at least one second conductive path connecting said clock terminal to said at least one latch;
• said at least one first and second conductive paths being approximately equal in length.

An integrated circuit memory device comprising:

• at least one data terminal for using an externally applied data signal for storage in a storage array of said memory circuit;
• a clock terminal for receiving an externally applied clock signal;
• at least one latch for latching in data received at said at least one data terminal in accordance with a clock signal received at said terminal and having an output for providing a data signal to said storage array;
• at least one first conductive path connecting said at least one data terminal to said latch;
• and
• at least one second conductive path connecting said clock terminal to said at least one latch;
• wherein a portion of each of said first and second conductive paths where said paths connected to said at least one latch are co-linear.

A memory module comprising:

• a mounting substrate;
• and
• a plurality of memory devices provided on said substrate, at least one of said memory devices comprising:
• at least one data terminal for using an externally applied data signal for storage in a storage array of said memory circuit;
• a clock terminal for receiving an externally applied clock signal;
• at least one latch for latching in data received at said at least one data terminal in accordance with a clock signal received at said terminal and having an output for providing a data signal to said storage array;
• at least one first conductive path connecting said at least one data terminal to said latch;
• and
• at least one second conductive path connecting said clock terminal to said at least one latch;
• said at least one first and second conductive paths being approximately equal in length.

A method of fabricating a data capture circuit for an integrated circuit, said method comprising:

• forming a latch circuit within said integrated circuit;
• forming a clock terminal for receiving an externally applied clock signal;
• forming at least one first conductive path connecting said at least one data terminal to said at least one latch;
• forming said at least one second conductive path connecting said clock terminal to said at least one latch;
• and
• arranging the path length of said formed first and second conductive paths to be approximately equal.