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US 2002/0118202 A1Published application
Same tile method
Assignee3Dlabs Inc., Ltd.
InventorDavid Robert Baldwin
Life of this patent
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Abstract
A tile-oriented graphics processing system in which an additional level of caching is provided locally, at the output of a patch-processing graphics computation block. This additional local storage buffers the current tile, so that repeated accesses to the same tile can avoid pipelining delays connected with access to the main cache. (Even an on-chip cache, in a large chip, can impose access delays which are significant in relation to the computation speeds involved.)
Claims4
A graphics processing method, comprising the steps of:
- selectably saving entire two-dimensional tiles of data, from the output of a graphics computational unit, in a dedicated same-tile buffer;
- and
- selectably making the contents of said same-tile buffer available for a data input to said unit.
A graphics processing method, comprising the steps of:
- (a.) selectably merging data outputs from a graphics computational unit with data retrieved from a cache;
- and
- (b.) selectably saving two-dimensional tiles of data, from the output of a graphics computational unit, in a dedicated same-tile buffer;
- and
- (c.) selectably making the contents of said same-tile buffer available for a data input to said unit.
2 more elements
Dependencies are inferred from the claim text.