Synchronized image display and buffer swapping in a multiple display environment
AssigneeSilicon Graphics, Inc.
InventorsShrijeet Mukherjee, Kanoj Sarcar, James Tornes
Life of this patent
Estimating the term…
Abstract
Ag system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
Claims12
A graphics system for generating synchronized images comprising:
- a plurality of slave processors;
- a master processor for synchronizing generation of a common scene by said plurality of slave processors;
- a synchronization module associated with said master processor;
- a plurality of device drivers for exchanging synchronization commands between said master processor and said plurality of slave processors, each device driver being associated with one of said plurality of slave processors;
- a timing signal provider for propagating a time synchronization signal to said plurality of slave processors from a synchronization signal generator associated with said master processor;
- at least one graphics processor associated with each slave processor for producing pixels in synchronization with the time synchronization signal;
- and
- a communications link connecting said master processor to each of said plurality of slave processors to provide simultaneous communication of a synchronization command to each of said plurality of slave processors.
A method for image display synchronization, the method comprising the steps of:
- (a) providing a time synchronization signal to each of a plurality of slave processors so that a plurality of graphics processors associated with said slave processors display pixels at approximately the same rate;
- (b) issuing a first command from a master processor to said plurality of slave processors to disable interrupts to said plurality of graphics processors;
- and
- (c) issuing a second command from said master processor to said plurality of slave processors to cause each of said slave processors to execute vertical retrace at a specified line.
Dependencies are inferred from the claim text.