Synchronization of vertical retrace for multiple participating graphics computers
AssigneeSilicon Graphics, Inc.
InventorsShrijeet Mukherjee, Kanoj Sarcar, James Tornes
Life of this patent
Estimating the term…
Abstract
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
Claims7
A method for image display synchronization, the method comprising the steps of:
- (a) synchronizing a master clock source associated with a master processor and a plurality of slave clock sources, each slave clock source being associated with a corresponding one of a plurality of slave processors, wherein said synchronizing step (a) determines a correction factor;
- (b) determining a master time for vertical retrace based on the length of a frame and said master clock source;
- (c) determining a slave vertical retrace time for each of said plurality of slave processors, wherein said slave vertical retrace time is a function of said master time for vertical retrace and said correction factor;
- (d) transmitting said slave vertical retrace time to each of said plurality of slave processors;
- and
- (e) executing vertical retrace at each of said plurality of slave processors when the slave clock source associated with each slave processor reaches said determined slave vertical retrace time.
A system for image display synchronization, comprising:
- a master clock source associated with a master processor;
- a plurality of slave clock sources, each slave clock source being associated with a corresponding one of a plurality of slave processors;
- a synchronization module for determining a slave vertical retrace time for at least one of said plurality of slave processors;
- and
- a communications link for transmitting said slave vertical retrace time to at least one of said plurality of slave processors, wherein each of said plurality of slave processors executes vertical retrace when said corresponding slave clock source reaches said determined slave vertical retrace time.
Dependencies are inferred from the claim text.