Swap buffer synchronization in a distributed rendering system
AssigneeSilicon Graphics, Inc.
InventorsShrijeet Mukherjee, Kanoj Sarcar, James Tornes
Life of this patent
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Abstract
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.
Claims7
A method for synchronizing swap ready in a multiprocessor graphics system, the method comprising the steps of:
- (a) synchronizing a master clock source associated with a master processor and a slave clock source associated with a slave processor;
- (b) determining at the master processor, a master swap status update time for the master processor and a slave swap status update time for said slave processor;
- (c) transmitting said slave swap status update time to said slave processor;
- (d) receiving at said master processor, a slave processor swap status after said slave clock source reaches said slave swap status update time;
- and
- (e) transmitting a command to swap buffers from said master processor to said slave processor when said slave processor has indicated that it is ready to perform a buffer swap.
A system for synchronizing swap ready in a multiprocessor graphics system, comprising:
- (a) a master clock source associated with a master processor and a plurality of slave clock sources, wherein each of said plurality of slave clock sources is associated with a corresponding one of a plurality of slave processors;
- and
- (b) a synchronization module for determining at the master processor, a slave swap status update time for at least one of said plurality of slave processors, wherein said slave swap status update time is used to synchronize swap ready in the multiprocessor graphics system;
- and
- (c) a communications link for transmitting a swap buffer command from said master processor to each of said plurality of slave processors when all of said plurality of slave processors have indicated that they are ready to perform a buffer swap.
Dependencies are inferred from the claim text.