LCD, and driving device and method thereof

An apparatus for driving an LCD, which includes an LCD panel having a plurality of data lines and gate lines, and which charges a specific pixel by (1) first charging the data of a pixel adjacent to the specific pixel and having the same polarity as the specific pixel to change the polarity of the corresponding pixel, and (2) second, charging the data of the specific pixel,

• the LCD comprising:
• a timing controller for receiving external image data, and outputting one vertical sync start signal based on a data-enable signal having an irregular output interval to control the output of the image data, the one vertical sync start signal having a generation interval associated with a blank interval of the data-enable signal;
• a data driver for converting the image data and outputting the converted image data to one of the data lines of the LCD panel;
• and
• a gate driver for applying a first gate-on voltage in a first charging to the gate line of the LCD panel, and a second gate-on voltage in a second charging to the gate line, based on the vertical sync start signal, and controlling display of the converted image data supplied from the data driver during the second charging, wherein the first gate-on voltage drives a previous line being most adjacent to and having the same polarity as a present line, and the second gate-on voltage drives the present line.

A method for driving an LCD that includes an LCD panel having a plurality of data lines and gate lines, which charges a specific pixel by (1) first charging the data of an pixel adjacent to the specific pixel and having the same polarity as the specific pixel to change the polarity of the corresponding pixel, and (2) second charging the data of the specific pixel,

• the method comprising:
• (a) receiving image data from an external image signal source and a data-enable signal for controlling output of the image data;
• (b) checking whether the data-enable signal has been received, sequentially recording the image data on a predetermined number of built-in memories upon receiving the data-enable signal, sequentially extracting the recorded image data, and generating an internal data-enable signal upon extraction of the image data to output a vertical sync start signal having a generation interval associated with a blank interval of the data-enable signal;
• (c) applying a voltage corresponding to the image data to the data lines;
• and
• (d) sequentially applying both a first gate-on voltage and a second gate-on voltage based on the vertical sync start signal, wherein the first gate-on voltage drives a previous line being most adjacent to and having the same polarity as the present line, and the second gate-on voltage drives the present line.