High noise rejection voltage-controlled ring oscillator architecture

A ring oscillator circuit, comprising:

• a plurality of differential delay cells interconnected in a ring configuration, wherein each differential delay cell is connected to a voltage supply and to a ground and comprises:
• first and second input transistors for receiving a differential input signal;
• a first current source connected between the first input transistor and the voltage supply;
• a second current source connected between the second input transistor and the voltage supply;
• a third current source connected between the first and second input transistors and the ground;
• a first load device connected between the first and third current sources;
• and
• a second load device connected between the second and third current sources.

A voltage-controlled oscillator circuit, comprising:

• a plurality of differential delay circuits interconnected in a ring configuration, wherein each differential delay circuit is coupled to first and second power supply terminals and comprises:
• first and second input transistors for receiving a differential input signal;
• first and second load transistors coupled in parallel with the first and second input transistors, respectively;
• a first current source coupled between the first input transistor and the first power supply terminal;
• a second current source coupled between the second input transistor and the first power supply terminal;
• and
• a third current source coupled between the first and second input transistors and the second power supply terminal.

A voltage-controlled oscillator circuit, comprising:

• a plurality of differential delay cells interconnected in a ring configuration, wherein each differential delay cell is connected to a voltage supply and to a ground and comprises:
• first and second input transistors for receiving a differential input signal;
• a first current source connected between the first input transistor and the voltage supply;
• a second current source connected between the second input transistor and the voltage supply;
• a third current source connected between the first and second input transistors and the ground;
• a first load device connected between the first and third current sources;
• and
• a second load device connected between the second and third current sources.

A differential delay circuit coupled to first and second power supply terminals, comprising:

• first and second input transistors for receiving a differential input signal;
• first and second load transistors coupled in parallel with the first and second input transistors, respectively;
• a first current source coupled between the first input transistor and the first power supply terminal;
• a second current source coupled between the second input transistor and the first power supply terminal;
• and
• a third current source coupled between the first and second input transistors and the second power supply terminal.

A differential delay circuit connected to a voltage supply and to a ground, comprising:

• first and second input transistors for receiving a differential input signal;
• a first current source connected between the first input transistor and the voltage supply;
• a second current source connected between the second input transistor and the voltage supply;
• a third current source connected between the first and second input transistors and the ground;
• a first load device connected between the first and third current sources;
• and
• a second load device connected between the second and third current sources.

A method of minimizing the coupling of noise sources from voltage and ground lines to a differential delay circuit, comprising the steps of:

• supplying power to first and second current sources from a first power supply terminal;
• supplying power to a third current source from a second power supply terminal;
• generating first, second and third currents from respective first, second and third current sources;
• sinking a current from the first current source to a first terminal of a first input transistor;
• sinking a current from the first current source to a first terminal of a first load transistor;
• sinking a current from the second current source to a first terminal of a second input transistor;
• sinking a current from the second current source to a first terminal of a second load transistor, and
• sinking a plurality of currents from the third current source to a second terminal of each of the plurality of first and second input and load transistors.