Reference clock generation system and device
AssigneeRohm Co., Ltd.
InventorsMasayu Fujiwara, Yasunori Kawamura
Life of this patent
Estimating the term…
Abstract
A clock generation system having a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock. The frequency division ratios are distributed such that, at least in the PLL circuit stages other than the first stage, the S/N ratios of the respective PLL circuit stages are smaller than the S/N ratio of the noise floor associated with the clock generation system.
Claims10
A clock generation system for generating, from a given first clock having a first clock frequency, a second clock having a second clock frequency which is related to said first clock frequency by a predetermined ratio, said clock generation system comprising:
- a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock, each of said PLL circuit stages having
- a first frequency divider for frequency dividing the input thereto;
- a second frequency divider for frequency dividing the output of said PLL circuit stage;
- a phase comparator for comparing said frequency divided output of said first frequency divider and the frequency divided output of said second frequency divider;
- a filter for filtering the output of said comparator;
- and
- a voltage controlled oscillator controlled by the output of said filter for supplying said second frequency divider with a signal having a controlled frequency, wherein
- said first and second frequency dividers are adapted to perform frequency division assigned to said PLL circuit stage.
A clock generation device built in an integrated circuit (IC) chip for generating, from a given first clock having a first clock frequency, a second clock having a second clock frequency which is related to said first clock frequency by a predetermined ratio, said clock generation device comprising:
- a multiplicity of PLL circuit stages connected in series such that frequency division ratios are distributed over said respective PLL circuit stages to attain said predetermined ratio, with the first PLL circuit stage receiving said first clock and the last PLL circuit stage outputting said second clock, each of said PLL circuit stages having
- a first frequency divider for frequency dividing the input thereto;
- a second frequency divider for frequency dividing the output of said PLL circuit stage;
- a phase comparator for comparing said frequency divided output of said first frequency divider and the frequency divided output of said second frequency divider;
- a filter for filtering the output of said comparator;
- and
- a voltage controlled oscillator controlled by the output of said filter for supplying said second frequency divider with a signal having a controlled frequency, wherein
- said first and second frequency dividers are adapted to perform frequency division assigned to said PLL circuit stage.
Dependencies are inferred from the claim text.