Negative voltage boosting circuit
AssigneeNEC Corporation
InventorMasamichi Ido
Life of this patent
Estimating the term…
Abstract
In a negative voltage boosting circuit in which plural boosting unit circuits each of which includes a MOS transistor for transferring charge one end of the source or the drain of which is connected to an input terminal and the other end of the source or the drain of which is connected to an output terminal for boosting negative voltage are connected in series between the input terminal and the output terminal for generating negative voltage at the output terminal, a well region forming a channel region of the MOS transistor for transferring charge is biased by electric potential at the output terminal of at least a second boosting unit circuit in an output direction.
Claims7
A negative voltage boosting circuit including a MOS transistor for transferring charge one end of the source or the drain of which is connected to an input terminal and the other end of the source or the drain of which is connected to an output terminal in which plural boosting unit circuits for boosting negative voltage are connected in series between the input terminal and the output terminal for generating negative voltage at the output terminal, wherein:
- a well region forming a channel region of the MOS transistor for transferring charge is biased by electric potential at the output terminal of at least a second boosting unit circuit in an output direction.
A negative voltage boosting circuit, wherein:
- in the boosting unit circuit except the first boosting unit circuit connected to the input terminal and the last boosting unit circuit connected to the output terminal, the gate of the MOS transistor for transferring charge is connected to the output terminal and one end of a capacitative element;
- a clock signal is applied to the other end of the capacitative element;
- and
- the clock signals applied to the adjacent boosting unit circuits are out of phase.
Dependencies are inferred from the claim text.