Integrated circuit and method for minimizing clock skews
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
Estimating the term…
Abstract
An integrated circuit interconnection comprising a transmission line having a low characteristic impedance, and including a first end and a second end. A driver is coupled to the first end of the transmission line, and the transmission line is terminated with a current sense amplifier having an input impedance corresponding to the characteristic impedance of the transmission line. A plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements are connected at spaced intervals to the transmission line between the first and second ends.
Claims66
An integrated circuit interconnection comprising:
- a transmission line having a low characteristic impedance, said transmission line including a first end and a second end;
- a driver coupled to the first end of said transmission line;
- a termination at the second end of said transmission line having an impedance corresponding to the characteristic impedance of said transmission line;* and
- a plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements, said components being connected at spaced intervals to said transmission line between said first and second ends.
An integrated circuit interconnection for minimizing clock skews comprising:
- a transmission line having a low characteristic impedance, said transmission line including a first end and a second end;
- a driver coupled to the first end of said transmission line;
- a termination at the second end of said transmission line having an impedance corresponding to the characteristic impedance of said transmission line for reducing ringing and reflections, said termination including a current sense amplifier coupled to the second end of the transmission line;
- and
- a plurality of components selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements, said components being connected at spaced intervals to said transmission line between said first and second ends for changing the propagation constant and delay time of said transmission line.
A method for minimizing clock skews on integrated circuit interconnections comprising the steps of:
- providing a transmission line having a low characteristic impedance, said transmission line including a first end and a second end;
- coupling a driver to the first end of said transmission line;
- coupling the second end of the transmission line to a current sense amplifier having an input impedance corresponding to the characteristic impedance of said transmission line for reducing ringing and reflections;
- and
- connecting a plurality components at spaced intervals to said transmission line between said first and second ends for changing the propagation constant and delay time of said transmission line, said components being selected from the group consisting of capacitive elements, inductive elements and a combination of capacitive and inductive elements.
Dependencies are inferred from the claim text.