US 2002/0118054 A1Published application

Delay lock loop circuit, varable delay circuit, and recording signal compensating circuit

AssigneeSony Corporation

InventorMasaki Endo

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Abstract

The present invention is intended to provide a delay lock loop circuit which is capable of providing a minute delay amount with stability regardless of the variations in delay amount due to variations in temperature and power supply voltage for example and process conditions. On the basis of a up/down control signal from a delay amount detector, count value is counted from initial setting value up to maximum setting value or down to minimum setting value. When the count value has reached the maximum or minimum value, another count value is counted up and down, thereby cutting the noise component of the up/down control signal. Consequently, regardless of the variation in delay amount due to a delay line, a delay lock detector to which the latter count value is supplied operates normally, thereby outputting with stability a reference delay step count for obtaining a delay of 1T.

Claims12

Dependent claims

A delay lock loop circuit comprising:

a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data;
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, said sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of said third pulse data and, when said count value has reached said maximum value and said minimum value, setting a next count value to said initial value, said up/down counter executing a count-up operation at a rising edge of said third pulse data when said count value of said sub counter is said maximum value and a count-down operation when said count value is said minimum value;
a delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter;
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal;
and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count.

3 more elements

A variable delay circuit comprising:

a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data,
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, said sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of said third pulse data and, when said count value has reached said maximum value and said minimum value, setting a next count value to said initial value, said up/down counter executing a count-up operation at a rising edge of said third pulse data when said count value of said sub counter is said maximum value and a count-down operation when said count value is said minimum value,
a first delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter,
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said first delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which said clock signal is supplied, for multiplying said reference delay step count with a delay rate;
and
a second delay means, configured in substantially a same manner as said first delay means, for delaying inputted data on the basis of a delay step count set by said delay step count setting means.

6 more elements

A recording signal compensating circuit for recording data to a disk recording medium in accordance with a recording pulse obtained by synthesizing a leading pulse, a burst pulse, and a trailing pulse, comprising:

a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data,
an up/down counter having a sub counter, to a count value of which an initial value, a maximum value, and a minimum value are set, said sub counter executing at least one of a count-up operation and a count-down operation on the basis of up/down control signal at a rising edge of said third pulse data and, when said count value has reached said maximum value and said minimum value, setting a next count value to said initial value, said up/down counter executing a count-up operation at a rising edge of said third pulse data when said count value of said sub counter is said maximum value and a count-down operation when said count value is said minimum value,
a first delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter,
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said first delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means to which said clock signal is supplied, for multiplying said reference delay step count with a delay rate;
a second delay means, configured in substantially a same manner as said first delay means, for delaying inputted data on the basis of a delay step count set by said delay step count setting means;
a leading pulse varying means for varying a pulse width of said leading pulse by delaying a leading edge position of said leading pulse;
and
a trailing pulse varying means for varying a pulse width of said trailing pulse by delaying a trailing edge position of said trailing pulse.

8 more elements

A delay lock loop circuit comprising:

a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data;
an up/down counter having
a first counter for executing a count-up operation at a rising edge of said third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting said count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted, and
a third counter for executing a count-up operation only when said up/down control signal is logically low at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted,
said up/down counter executes, when said reset signal is inputted, a count/up operation if the count value obtained by said second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by said third counter is higher than said preset value N;
a delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter;
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal;
and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count.

7 more elements

A variable delay circuit comprising:

a reference delay step count outputting means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data,
an up/down counter having
a first counter for executing a count-up operation at a rising edge of said third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting said count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted, and
a third counter for executing a count-up operation only when said up/down control signal is logically low at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted,
said up/down counter executes, when said reset signal is inputted, a count/up operation if the count value obtained by said second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by said third counter is higher than said preset value N,
a first delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter,
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said first delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which said clock signal is supplied, for multiplying said reference delay step count with a delay rate;
and
a second delay means, configured in substantially a same manner as said first delay means, for delaying inputted data on the basis of a delay step count set by said delay step count setting means.

10 more elements

a reference delay step count output means having
a dividing means for generating, on a clock signal, first pulse data, second pulse data having a period greater than that of said first pulse data, and third pulse data having a period greater than that of said second pulse data,
an up/down counter having
a first counter for executing a count-up operation at a rising edge of said third pulse data and, if a count value has exceeded a preset value M (an integer higher than 0), outputting a reset signal and resetting said count value,
a second counter for executing a count-up operation only when an up/down control signal is logically high at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted, and
a third counter for executing a count-up operation only when said up/down control signal is logically low at a rising edge of said third pulse data and resetting a count value when said reset signal is inputted,
said up/down counter executes, when said reset signal is inputted, a count/up operation if the count value obtained by said second counter is higher than preset value N (an integer higher than 0 and lower than M) and a count-down operation if the count value obtained by said third counter is higher than said preset value N,
a first delay means for delaying said first pulse data in accordance with the number of delay steps based on a count output of said up/down counter,
a delay amount detecting means for determining which of a rising edge of said second pulse data and a rising edge of an output pulse of said first delay means comes first and outputting, on the basis of a result of this determination, said up/down control signal, and
a delay lock detecting means for comparing a current count value with a past count value of said up/down counter at a rising edge of said third pulse data to determine whether or not a delay amount is locked, selecting one of said current count value and said past count value, and outputting the selected count value as a reference delay step count;
a delay step count setting means, to which said clock signal is supplied, for multiplying said reference delay step count with a delay rate;
a second delay means, configured in substantially a same manner as said first delay means, for delaying inputted data on the basis of a delay step count set by said delay step count setting means;
a leading pulse varying means for varying a pulse width of said leading pulse by delaying a leading edge position of said leading pulse;
and
a trailing pulse varying means for varying a pulse width of said trailing pulse by delaying a trailing edge position of said trailing pulse.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/084,789Filed 25 Feb 2002
Priority: JP P2001-05043326 Feb 2001
Published: 29 Aug 2002
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G11B 20/1403
Using self-clocking codes: characterised by the use of two levels
H03L 7/0814
And where no voltage or current controlled oscillator is used: the phase shifting device being digitally controlled
H03L 7/0816
And where no voltage or current controlled oscillator is used: the controlled phase shifter and the frequency- or phase-detection arrangement…
H03L 7/095
Concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal: using a lock detector