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US 2002/0118053 A1Published application
PLL device
AssigneeSanyo Electric Co., Ltd.
InventorsYasuaki Sumi, Katsu Horikoshi, Hisayoshi Uchiyama
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AssigneeSanyo Electric Co., Ltd.
InventorsYasuaki Sumi, Katsu Horikoshi, Hisayoshi Uchiyama
Estimating the term…
The PLL device includes means (6) for generating a, plurality of reference signals (FR1, FR2, FR3, FR4) having mutually differing phases, a variable frequency divider (11, 12, 13, 14) for dividing, in synchronization with the phases of a plurality of the reference signals, a frequency of an output signal (FO) of a voltage-controlled oscillator (15) that produces a signal having a frequency responsive to a control voltage (CV) supplied to generate a plurality of feedback signals (FV1, FV2, FV3, FV4) having mutually differing phases, phase comparators (7, 17, 8, 18, 9, 19, 10, 20) for comparing phases between the reference signals and the feedback signals corresponding to the reference signals respectively to produce a plurality of error signals (ER1, ER2, ER3, ER4), a low-pass filter (21) for filtering the error signals output from the phase comparators to produce the control voltage, and a control means (16, 26, 27) for controlling the number of the phase comparators that output the error signals to the low-pass filter in accordance with a phase difference between at least one of a plurality of the feedback signals and the reference signal corresponding to the one of a plurality of the feedback signals.
A PLL device comprising:
A PLL device according to claim 5, in which the second phase comparator (58, 59, 60) is provided with a first delay circuit (40) for delaying an incoming reference signal and a second delay circuit (47) for delaying an incoming feedback signal.
A PLL device comprising:
A PLL device according to claim 8, in which at least one of a plurality of the second phase comparators is provided with a plurality of selectable delay circuits (60, 61, 62, 74, 75, 76) for delaying an input signal.
A PLL device according to claim 9, in which a plurality of the delay circuits are comprised of inverters connected in series.
A PLL device according to claim 9 or 10, in which selection circuits are connected to outputs of a plurality of the delay circuits so that an output of any delay circuit connected to a selection circuit supplied with a specific control signal can be selected.
A PLL device according to any one of claims 9 to 11, in which a plurality of the delay circuits comprise a plurality of delay circuits (60, 61, 62) for delaying an incoming reference signal and a plurality of delay circuits (74, 75, 76) for delaying an incoming feedback signal.
A PLL device comprising:
A PLL device according to claim 13, in which the outputting periods do not overlap with each other.
A PLL device according to claim 14, in which a suspension period (R1, R2, R3, R4, R5) during which productions of the error signals are all stopped is interposed between neighboring outputting periods.
A PLL device according to any one of claims 13 to 15, in which rising or falling edges of the reference signals are situated at approximately enters of the outputting periods respective
A PLL device comprising:
A PLL device comprising:
Dependencies are inferred from the claim text.