US 2002/0118043 A1 · Single to differential input buffer circuit

Abstract

The invention relates to methods and apparatus that efficiently convert a single-ended input signal to a differential output signal at high speeds so that a non-inverted differential output and an inverted differential output maintain a true differential phase relationship even at relatively high frequencies of input data. A single-to-differential input buffer circuit includes multiple paths from the input signal to the differential output signals and transitions relatively quickly from a first state to a second state in response to a change in state of the input signal. An input phase-splitting stage of the single-to-differential input buffer circuit includes cross-coupled positive feedback to dramatically increase the frequency response of the phase-splitting stage. Advantageously, the single-to-differential input buffer also includes cross-coupled transistors that compensate for a portion of the positive feedback to prevent latch-up and yet retain the speed advantages of the cross-coupled positive feedback. One embodiment maintains the transistors of the input stage in a linear region.

Claims17

Dependent claims

A single-to-differential input buffer circuit, comprising:

a single-ended input terminal;
an emitter coupled differential input circuit having a first differential input connected to the single-ended input terminal and a second differential input connected to a biasing voltage;
a cross-coupled transistor circuit connected to the emitter coupled differential input circuit, the cross-coupled transistor circuit configured to provide positive feedback to the emitter coupled differential input circuit;
a positive feedback compensation circuit coupled to the cross-coupled transistor circuit, the positive feedback compensation circuit configured to divert at least a portion of the positive feedback from the emitter coupled differential input circuit in response to a first condition;
and
differential outputs coupled to the cross-coupled transistor circuit.

3 more elements

A buffer, comprising:

a first input terminal;
a second input terminal;
an emitter coupled differential input circuit, including a first transistor having a first base, a first collector, and a first emitter, the first base coupled to the first input terminal, and a second transistor having a second base, a second collector, and a second emitter, the second base coupled to the second input terminal;
a third transistor having a third base, a third collector, and a third emitter, the third emitter coupled to the first base, and the third collector coupled to a voltage source via a first resistor;
a fourth transistor having a fourth base, a fourth collector, and a fourth emitter, the fourth based coupled to the third collector, the fourth emitter coupled to the second base, and the fourth collector coupled to the third base and coupled to the voltage source via a second resistor;
a fifth transistor having a fifth base, a fifth collector, and a fifth emitter, the fifth base coupled to the first collector and the third emitter, the fifth collector coupled to the third base, and the fifth emitter coupled to a current sink circuit;
a sixth transistor having a sixth base, a sixth collector, and a sixth emitter, the sixth base coupled to the second collector and the fourth emitter, the sixth collector coupled to the fourth base, and the sixth emitter coupled to the current sink circuit;
a first buffering circuit coupled to the third collector;
a second buffering circuit coupled to the fourth collector;
a non-inverting output coupled to the first buffering circuit;
and
an inverting output coupled to the second buffering circuit.

9 more elements

Dependencies are inferred from the claim text.

Single to differential input buffer circuit

Life of this patent

Single to differential input buffer circuit

Life of this patent

Abstract

Claims17