Semiconductor integrated circuit device, method of testing semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device

A method of manufacturing a memory circuit which has a plurality of signal nodes to which an operation control signal for controlling memory selecting operation and an operation timing signal are supplied, and in which word-line selecting operation, sense amplifier operation following the word-line selecting operation, memory selecting operation including data transmitting operation, and the termination of the memory selecting operation including the termination of the word-line selecting operation are effected on the basis of the operation control signal, a reference timing of the internal operation of said memory circuit being set by the operation timing signal, said memory circuit having a defect remedy circuit, comprising:

• a first step of preparing a semiconductor integrated circuit substrate on which said memory circuit and said defect remedy circuit are formed;
• a second step of testing response characteristics of said memory circuit by a testing apparatus by setting a frequency of the timing signal to a level lower than that at the time of normal operation in correspondence with the performance of said testing apparatus, by controlling a period of operation of said memory circuit through a combination of the timing signal and a timing signal used exclusively for testing, and by controlling the period of operation;
• a third step of determining a portion of said memory circuit whose defect is to be remedied on the basis of a result of the testing of the response characteristics;
• and
• a fourth step of remedying by said defect remedy circuit the portion whose defect is to be remedied and which has been determined in the third step.