# US 2002/0118006 A1 · Phase frequency detector

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- Number: US 2002/0118006 A1
- Document ID: US20020118006A1
- Status: Published application
- Kind: A1
- Application number: 09/873,895
- Filed: 2001-06-04
- Published: 2002-08-29
- Earliest claimed: 2000-06-02
- Inventors: Syed K. Enam; Masoud Djafari; Duke T. Tran
- Web page: https://patentgrep.com/patent/US20020118006A1

## CPC

- H04L 7/0338: {the correction of the phase error being performed by a feed forward loop}
- H03D 7/1433: {using bipolar transistors (H03D7/145 takes precedence)}
- H03D 7/1441: {using field-effect transistors (H03D7/145 takes precedence)}
- H03D 7/1458: {Double balanced arrangements, i.e. where both input signals are differential}
- H03F 3/45085: {Long tailed pairs (H03F3/45112, H03F3/45139 take precedence)}
- H03K 19/01812: {with at least one differential stage}
- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/0896: {the current generators being controlled by differential up-down pulses}
- H03L 7/091: the phase or frequency detector using a sampling device (H03L7/087 takes precedence)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/10: for assuring initial synchronisation or for broadening the capture range
- H03L 7/14: for assuring constant frequency when supply or correction voltages fail
- H04J 3/0608: {Detectors therefor, e.g. correlators, state machines}
- H04L 1/242: {by comparing a transmitted test signal with a locally generated replica}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L 25/0272: {Arrangements for coupling to multiple lines, e.g. for differential transmission}
- H04L 25/0274: {Arrangements for ensuring balanced coupling}
- H04L 25/0278: {Arrangements for impedance matching}
- H04L 25/028: {Arrangements specific to the transmitter end}
- H04L 25/0282: {Provision for current-mode coupling}
- H04L 25/0292: {Arrangements specific to the receiver end}
- H04L 25/0294: {Provision for current-mode coupling}
- H04L 25/05: Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
- H03D 2200/0033: Current mirrors
- H03D 2200/0043: Bias and operating point
- H03D 2200/0047: Offset of DC voltage or frequency
- H03F 2203/45592: the IC comprising one or more buffer stages other than emitter or source followers between the input signal leads and input leads of the dif amp, e.g. inverter stages
- H03F 2203/45612: the IC comprising one or more input source followers as input stages in the IC
- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- H04L 7/0337: {Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals}
- H04L 25/0266: {Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling}
- H04L 25/0286: {Provision of wave shaping within the driver (wave shaping per se H04L25/03834)}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)
- H03F: AMPLIFIERS
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)

## Abstract

A phase frequency detector in a clock multiply unit of a serial transmitter detects differences in phase and frequency between a reference clock and an internal clock generated by the clock multiply unit. The phase frequency detector includes a reset circuit which increases the sensitivity and reliability of the phase frequency detector, thereby allowing the phase frequency detector to operate at high speeds. The phase frequency detector produces a pair of output signals which have rising edges corresponding to rising edges of the reference clock and the internal clock respectively. The reset circuit activates a reset signal to reset the phase frequency detector when the output signals are both at logic high and continues to activate the reset signal until both of the output signals reach logic low.

## Claims

### Claim 1

A method of performing phase frequency detection, said method comprising:
generating a first pulse which transitions from logic low to logic high at rising edges of a reference clock;
generating a second pulse which transitions from logic low to logic high at rising edges of a generated clock; and
resetting the first pulse and the second pulse to logic low when both the first pulse and the second pulse are logic high, wherein the resetting occurs until both the first pulse and the second pulse have transitioned to logic low.

### Claim 2 (depends on 1)

The method of claim 1, wherein the first pulse and the second pulse provides an indication of the frequency difference between the reference clock and the generated clock.

### Claim 3

A phase frequency detector comprising:
a first flip-flop configured to receive a reference clock and to produce a first output;
a second flip-flop configured to receive an internal clock and to produce a second output; and
a reset circuit configured to receive the first output and the second output and to produce a reset signal which resets the first flip-flop and the second flip-flop, wherein the reset signal is activated when the first output and the second output are both logic high and remains activated until both the first output and the second output reach logic low.

### Claim 4 (depends on 3)

The phase frequency detector of claim 3, wherein the first output transitions high at rising edges of the reference clock, the second output transitions high at rising edges of the internal clock, and a difference between the first output and the second output indicates a phase difference between the reference clock and the internal clock.

### Claim 5 (depends on 3)

The phase frequency detector of claim 3, wherein the phase frequency detector is part of a phase locked loop used to generate a transmitter clock with a frequency that is a multiple of the reference clock frequency, and the internal clock is a sub-multiple of the transmitter clock.

### Claim 6

A detector circuit comprising:
means for generating a first signal to indicate that an internal clock is slower than a reference clock;
means for generating a second signal to indicate that the internal clock is faster than the reference clock; and
means for generating a reset signal to reset the first signal and the second signal, wherein the reset signal is activated when the first signal and the second signal are logic high and remains activated until the first signal and the second signal are logic low.

### Claim 7 (depends on 6)

The detector circuit of claim 6, wherein differences in pulse-widths of the first signal and the second signal are proportional to differences in frequencies between the internal clock and the reference clock.

### Claim 8

A method of performing phase frequency detection, said method comprising:
generating a first differential signal which transitions from a first logic level to a second logic level based on the phase and frequency of a reference clock;
generating a second differential signal which transitions from a first logic level to a second logic level based on the phase and frequency of a generated clock; and
resetting the first differential signal and the second differential signal to the first logic level when both the first differential signal and the second differential signal are at the second logic level, wherein the resetting occurs until both the first differential signal and the second differential signal have transitioned to the first logic level; and
comparing the first and second differential signals to generate a differential control voltage which drives a differential voltage controller oscillator.

### Claim 9 (depends on 8)

The method of claim 8, wherein the first and second differential signals transition from the first logic level to the second logic level based on rising edges of the respective reference and generated clocks.

### Claim 10

A method of performing phase frequency detection, said method comprising:
generating a first pulse which transitions from logic low to logic high at rising edges of a reference clock;
generating a second pulse which transitions from logic low to logic high at rising edges of a generated clock; and
resetting the first pulse and the second pulse to logic low when both the first pulse and the second pulse are logic high, wherein the resetting occurs until both the first pulse and the second pulse have transitioned to logic low.