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US 2002/0117722 A1Published application
Semiconductor integrated circuit device
AssigneeHitachi, Ltd.
InventorsKenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
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AssigneeHitachi, Ltd.
InventorsKenichi Osada, Masataka Minami, Shuji Ikeda, Koichiro Ishibashi
Estimating the term…
Prior known static random access memory (SRAM) cells are required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to occurrence of a problem as to the difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supplying power to the substrate are formed in parallel to word lines in such a manner that one regions is provided per group of thirty two memory cell rows or sixty four cell rows.
A semiconductor memory device comprising a first inverter including a first N-channel metal oxide semiconductor (MOS) transistor and a first P-channel MOS transistor, a second inverter including a second N-channel MOS transistor and a second P-channel MOS transistor with an input terminal being connected to an output terminal of said first inverter and with an output terminal being connected to an input terminal of said first inverter, a third N-channel MOS transistor having a source connected to the output terminal of said first inverter and a drain connected to a first bit line and also a gate connected to a word line, and a fourth N-channel MOS transistor having a source connected to the output terminal of said second inverter and a drain connected to a second bit line plus a gate connected to a word line, wherein the first and third N-channel MOS transistors are formed in a first P-type well region, its diffusion layer having an outer shape consisting essentially of straight lines including a straight line portion with a maximal length extending parallel to a boundary relative to a first N-type well region with the first and second P-channel MOS transistors formed therein and also being linear symmetrical with respect to a straight line defined as a center line extending parallel to the boundary, and wherein the second and fourth N-channel MOS transistors are formed in a second P-type well region, its diffusion layer having an outer shape consisting essentially of straight lines including a straight line portion with a maximal length extending parallel to the boundary relative to the first n-type well region with said first and second P-channel MOS transistors formed therein and also being linear symmetrical with the straight line defined as the center line in parallel to the boundary.
A semiconductor memory device comprising:
A semiconductor device comprising first and second inverters with an output of each inverter being as an input of a remaining inverter, a first switch connected to a connection node between an output of the first inverter and an input of the second inverter, and a second switch connected to a connection node between an input of said first inverter and an output of said second inverter, wherein
A semiconductor memory device comprising:
Dependencies are inferred from the claim text.