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US 2002/0117704 A1Published application
Memory cell capacitors having an over/under configuration
AssigneeMicron Technology, Inc.
InventorFernando Gonzalez
Life of this patent
Estimating the term…
Abstract
Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.
Claims40
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a capacitor below a channel region of the access transistor, wherein the capacitor is coupled to the first source/drain region of the access transistor;
- wherein the capacitor is overlying at least a portion of a capacitor of a second memory cell;
- and
- wherein the second memory cell has an access transistor having a source/drain region coupled to the bit line.
3 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a capacitor coupled to the first source/drain region of the access transistor through an extension;
- wherein the extension is laterally adjacent a second capacitor of a second memory cell;
- and
- wherein the capacitor of the memory cell is underlying at least a portion of the second capacitor of the second memory cell.
3 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a first cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a second cell capacitor having a storage node laterally adjacent the extension of the first memory cell.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell;
- and
- wherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell.
2 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein the first memory cell further includes a first cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a second cell capacitor having a storage node laterally adjacent the extension of the first memory cell.
5 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein the first memory cell further includes a cell capacitor coupled to the first source/drain region of the first access transistor through an extension;
- and
- wherein the second memory cell further includes a cell capacitor interposed between the second access transistor and the cell capacitor of the first memory cell.
5 more elements
A memory device, comprising:
- a plurality of bit lines;
- a plurality of word lines;
- an array of memory cells, wherein the array of memory cells comprises:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the plurality of bit lines, and a gate coupled to a first word line of the plurality of word lines;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the plurality of word lines different from the first word line;
- wherein a cell capacitor of the first memory cell is underlying the first source/drain region of the first memory cell;
- and
- wherein the cell capacitor of the first memory cell is overlying at least a portion of a cell capacitor of the second memory cell.
5 more elements
A method of forming a pair of memory cells:
- forming a first insulative layer on the substrate;
- patterning the first insulative layer to define future first source/drain regions;
- forming a pair of first source/drain regions in the substrate;
- forming a first storage node coupled to a first one of the pair of first source/drain regions and forming an extension coupled to a second one of the pair of first source/drain regions, wherein the extension is isolated from the first storage node;
- forming a first cell dielectric layer overlying the first storage node and the extension;
- forming a first cell plate layer overlying the first cell dielectric layer;
- forming a second insulative layer overlying the first cell plate layer;
- exposing a portion of the extension;
- forming a second storage node coupled to the exposed portion of the extension and isolated from the first storage node and the first cell plate layer;
- forming a second cell dielectric layer overlying the second storage node;
- forming a second cell plate layer overlying the second cell dielectric layer;
- forming a third insulative layer overlying the second cell plate layer;
- cleaving the substrate, thereby exposing a surface of the substrate;
- planarizing the exposed surface of the substrate to expose the first source/drain regions;
- forming a first word line overlying at least a portion of the first one of the pair of first source/drain regions;
- forming a second word line overlying at least a portion of the second one of the pair of first source/drain regions;
- and
- forming a second source/drain region in the substrate interposed between the first word line and the second word line.
15 more elements
A method of forming a pair of memory cells:
- forming a first insulative layer on the substrate;
- patterning the first insulative layer to define future first source/drain regions;
- forming a pair of first source/drain regions in the substrate;
- forming a first storage node coupled to a first one of the pair of first source/drain regions and forming an extension coupled to a second one of the pair of first source/drain regions, wherein the extension is isolated from the first storage node;
- forming a first cell dielectric layer on the first storage node and the extension;
- forming a first cell plate layer on the first cell dielectric layer;
- forming a second insulative layer on the first cell plate layer;
- exposing a portion of the extension;
- forming a second storage node coupled to the exposed portion of the extension and isolated from the first storage node and the first cell plate layer;
- forming a second cell dielectric layer on the second storage node;
- forming a second cell plate layer on the second cell dielectric layer;
- forming a third insulative layer on the second cell plate layer;
- cleaving the substrate, thereby forming a cleaved surface of the substrate;
- planarizing the cleaved surface of the substrate to expose the first source/drain regions;
- forming a first word line on at least a portion of the first one of the pair of first source/drain regions;
- forming a second word line on at least a portion of the second one of the pair of first source/drain regions;
- and
- forming a second source/drain region in the substrate interposed between the first word line and the second word line.
15 more elements
A method of forming capacitors for a pair of memory cells, comprising:
- forming a first insulative layer on a substrate;
- removing a portion of the first insulative layer to expose first and second portions of the substrate;
- forming a first capacitor overlying the first insulative layer and coupled to the first portion of the substrate, wherein the first capacitor includes a storage node, a cell dielectric layer and a cell plate layer;
- forming a conductive extension coupled to the second portion of the substrate and isolated from the storage node of the first capacitor;
- forming a second capacitor overlying at least a portion of the first capacitor and coupled to the second portion of the substrate through the conductive extension, wherein the second capacitor includes a storage node, a cell dielectric layer and a cell plate layer.
2 more elements
A method of forming a pair of memory cells, comprising:
- forming a first insulative layer on a substrate;
- implanting particles in the substrate, thereby forming a stressed region below the first insulative layer;
- patterning the first insulative layer to expose first and second portions of the substrate;
- forming a first one of a pair of first source/drain regions in the first portion of the substrate;
- forming a second one of the pair of first source/drain regions in the second portion of the substrate;
- forming a second insulative layer on the first insulative layer;
- forming a first sacrificial layer on the second insulative layer;
- patterning the first sacrificial layer and the second insulative layer to expose the pair of first source/drain regions and at least a portion of the first insulative layer;
- forming a first conductive layer overlying the pair of first source/drain regions, the first insulative layer, the second insulative layer and the first sacrificial layer;
- removing a top portion of the first conductive layer to expose the first sacrificial layer, thereby defining a first storage node coupled to the first one of the pair of first source/drain regions and a conductive extension coupled to the second one of the pair of first source/drain regions;
- removing the first sacrificial layer;
- forming a first cell dielectric layer on the first storage node and the conductive extension;
- forming a second conductive layer on the first cell dielectric layer;
- forming a third insulative layer on the second conductive layer;
- removing a portion of the third insulative layer, the second conductive layer and the first cell dielectric layer to expose a portion of the conductive extension;
- insulating exposed sidewalls of the second conductive layer adjacent the exposed portion of the conductive extension;
- forming a fourth insulative layer on the third insulative layer and the exposed portion of the conductive extension;
- forming a second sacrificial layer on the fourth insulative layer;
- patterning the second sacrificial layer and the fourth insulative layer to re-expose the exposed portion of the conductive extension;
- forming a third conductive layer overlying the exposed portion of the conductive extension, the third insulative layer, the fourth insulative layer and the second sacrificial layer;
- removing a top portion of the third conductive layer to expose the second sacrificial layer, thereby defining a second storage node coupled to the exposed portion of the conductive extension;
- removing the second sacrificial layer;
- forming a second cell dielectric layer on the second storage node;
- forming a fourth conductive layer on the second cell dielectric layer;
- forming a fifth insulative layer on the fourth conductive layer;
- removing a portion of the substrate to expose the pair of first source/drain regions;
- forming a first word line on at least a portion of the first one of the pair of first source/drain regions;
- forming a second word line on at least a portion of the second one of the pair of first source/drain regions;
- and
- forming a second source/drain region in the substrate interposed between the first word line and the second word line.
27 more elements
A method of forming a pair of memory cells, comprising:
- forming a first layer of silicon dioxide on a substrate;
- forming a first layer of silicon nitride on the first layer of silicon dioxide;
- implanting particles in the substrate, thereby forming a stressed region below the first layer of silicon dioxide, wherein the particles are selected from the group consisting of hydrogen molecules, hydrogen ions, deuterium molecules and deuterium ions;
- patterning the first layer of silicon dioxide and the first layer of silicon nitride to expose first and second portions of the substrate;
- forming a first one of a pair of first source/drain regions in the first portion of the substrate;
- forming a second one of the pair of first source/drain regions in the second portion of the substrate;
- forming a second layer of silicon dioxide on the first layer of silicon nitride and the pair of first source/drain regions;
- forming a first layer of doped silicon dioxide on the second layer of silicon dioxide;
- patterning the first layer of doped silicon dioxide and the second layer of silicon dioxide to expose the pair of first source/drain regions and at least a portion of the first layer of silicon nitride;
- forming a first layer of conductively-doped polysilicon overlying the pair of first source/drain regions, the first layer of silicon nitride, the second layer of silicon dioxide and the first layer of doped silicon dioxide;
- removing a top portion of the first layer of conductively-doped polysilicon to expose the first layer of doped silicon dioxide, thereby defining a first storage node coupled to the first one of the pair of first source/drain regions and a conductive extension coupled to the second one of the pair of first source/drain regions;
- removing the first layer of doped silicon dioxide;
- forming a first cell dielectric layer on the first storage node and the conductive extension;
- forming a second layer of conductively-doped polysilicon on the first cell dielectric layer;
- forming a third layer of silicon dioxide on the second layer of conductively-doped polysilicon;
- forming a second layer of silicon nitride on the third layer of silicon dioxide;
- removing a portion of the second layer of silicon nitride, the third layer of silicon dioxide, the second layer of conductively-doped polysilicon and the first cell dielectric layer to expose a portion of the conductive extension;
- forming insulative spacers on exposed sidewalls of the second layer of conductively-doped polysilicon;
- forming a fourth layer of silicon dioxide on the second layer of silicon nitride, the insulative spacers and the exposed portion of the conductive extension;
- forming a second layer of doped silicon dioxide on the fourth layer of silicon dioxide;
- patterning the second layer of doped silicon dioxide and the fourth layer of silicon dioxide to re-expose the exposed portion of the conductive extension and to expose a portion of the second layer of silicon nitride;
- forming a third layer of conductively-doped polysilicon overlying the exposed portion of the conductive extension, the insulative spacers, the exposed portion of the second layer of silicon nitride, the fourth layer of silicon oxide and the second layer of doped silicon dioxide;
- removing a top portion of the third layer of conductively-doped polysilicon to expose the second layer of doped silicon dioxide, thereby defining a second storage node coupled to the exposed portion of the conductive extension;
- removing the second layer of doped silicon dioxide;
- forming a second cell dielectric layer on the second storage node;
- forming a fourth layer of conductively-doped polysilicon on the second cell dielectric layer;
- forming a third layer of doped silicon dioxide on the fourth layer of conductively-doped polysilicon;
- cleaving the substrate at the stressed regions, thereby exposing a surface of the substrate;
- planarizing the exposed surface of the substrate to expose the pair of first source/drain regions;
- forming a first word line on at least a portion of the first one of the pair of first source/drain regions;
- forming a second word line on at least a portion of the second one of the pair of first source/drain regions;
- and
- forming a second source/drain region in the substrate interposed between the first word line and the second word line.
30 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a container capacitor coupled to the first source/drain region of the access transistor;
- wherein the container capacitor is overlying at least a portion of a container capacitor of a second memory cell;
- and
- wherein the second memory cell has an access transistor having a source/drain region coupled to the bit line.
3 more elements
A memory cell, comprising:
- an access transistor having a first source/drain region and a second source/drain region, wherein the second source/drain region is coupled to a bit line;
- and
- a container capacitor coupled to the first source/drain region of the access transistor through an extension;
- wherein the extension is laterally adjacent a second container capacitor of a second memory cell;
- and
- wherein the container capacitor of the memory cell is underlying at least a portion of the second container capacitor of the second memory cell.
3 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a first cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor;
- and
- wherein the second memory cell further includes a second cell capacitor at least a portion of which is below the first cell capacitor.
2 more elements
A memory device, comprising:
- a first memory cell including a first access transistor having a first source/drain region, a second source/drain region coupled to a first bit line of the memory device, and a gate coupled to a first word line of the memory device;
- a second memory cell including a second access transistor having a first source/drain region, a second source/drain region coupled to the first bit line, and a gate coupled to a second word line of the memory device, wherein the second word line is different from the first word line;
- wherein the first memory cell further includes a cell capacitor below a channel region of the first access transistor and coupled to the first source/drain region of the first access transistor;
- and
- wherein the second memory cell further includes a cell capacitor interposed between a channel region of the second access transistor and the cell capacitor of the first memory cell.
2 more elements
Dependencies are inferred from the claim text.