Apparatus and method to reduce interrupt latency in shared interrupt systems

A method of handling interrupts in a computing apparatus having a plurality of devices that share a shared interrupt request line, each of said plurality of devices having a corresponding service routine including a core service portion comprising instructions for servicing the device in response to the device asserting an interrupt request signal on the shared interrupt request line, the method comprising the steps of:

• (a) enabling one device among said plurality of devices to be selected as a highest priority device;
• (b) indicating an order in which the service routines are to be dispatched for execution on the computing apparatus in response to an interrupt request signal being asserted on the shared interrupt request line, said order indicating that the service routine corresponding to the highest priority device is dispatched first, and that at least a portion of the other service routines are executed, as necessary, based on their respective positions in the order;
• (c) asserting a first interrupt request signal on the shared interrupt request line with one of said plurality of devices;
• (d) in response to step (c), initiating execution of at least one service routine on the computing apparatus, as necessary, based on the order of said service routines;
• and
• (e) executing said at least one service routine that was initiated in step (d) on the computing apparatus, as necessary, until the device that asserted the first interrupt service request is serviced by its corresponding service routine.

A computing apparatus comprising:

• (a) a memory for storing a plurality of machine instructions;
• (b) a shared interrupt request line;
• (c) a plurality of devices connected to the shared interrupt request line, including a device that is selected to be a highest priority device;
• (d) a respective service routine for each of said plurality of devices, each service routine comprising a portion of the plurality of machine instructions stored in the memory and including a core service portion comprising machine instructions for servicing a corresponding device in response to that device asserting an interrupt request signal on the shared interrupt request line;
• and
• (e) a processor for executing the plurality of machine instructions stored in the memory, causing functions to be performed in response to a first interrupt request signal asserted by one of said plurality of devices on the shared interrupt request line, said functions including:
• (i) determining a device from among said plurality of devices that asserted the first interrupt request signal;
• (ii) dispatching execution by the processor of the machine instructions comprising the core service portion of the service routine corresponding to the device that asserted the interrupt request signal;
• and
• (iii) enabling execution of the core service portion of the service routine to be interrupted in response to a subsequent interrupt request signal that is asserted on the shared interrupt request line by the highest priority device.