# US 2002/0103976 A1 · Adaptive dirty-block purging > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2002/0103976 A1 - Document ID: US20020103976A1 - Status: Published application - Kind: A1 - Application number: 09/771,098 - Filed: 2001-01-26 - Published: 2002-08-01 - Earliest claimed: 2001-01-26 - Assignees: Compaq Computer Corporation - Inventors: Simon C. Steely JR.; Nikolaos Hardavellas - Web page: https://patentgrep.com/patent/US20020103976A1 ## CPC - G06F 12/0817: using directory methods - G06F 12/0804: with main memory updating (G06F12/0806 takes precedence) - G06F 12/0822: {Copy directories (local copy tags for implementing a bus snooping protocol G06F12/0831)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An adaptive cache coherent purging protocol includes recognizing system performance, especially latency, is affected by when cache is purged. The occurrence of performance enhancing and degrading events regarding a cache are counted and compared to a threshold. When the threshold is triggered the cache becomes a candidate for purging. In an embodiment, a time out delay is implemented before actual purging occurs. When the threshold is not triggered but a cache event occurs, a fake time out delay is triggered and the count is adaptively either raised, lowered or set to zero in response to performance enhancing and/or degrading events. The effect is to make the actual purging more likely if the history of cache events indicates that the performance would be enhanced thereby or less likely if the history indicates that the performance would be degraded thereby. ## Claims ### Claim 1 A method for adaptively determining cache data candidates for purging, wherein physical cache memory is associated with a local component of a local node in a modular multiprocessor system having a of plurality interconnected processors, I/O ports, and memory, the method comprising the steps of: determining system performance enhancing and degrading events occurring with respect to purging cache data, first tracking performance enhancing events on the cache data, second tracking performance degrading events on the cache data, assessing the impact on system performance by the first and second trackings, and in response thereto, if performance would be enhanced, designating the cache data for purging. ### Claim 2 (depends on 1) The method as defined in claim 1 wherein the step of determining system enhancing and degrading events includes the steps of: recognizing that: some read-dirties and certain references by remote processors after a purge are enhancing event, and that some writes to the data by the local processor that owns the data and some writes after the data has been purged are performance degrading events. ### Claim 3 (depends on 1) The method as defined in claims 1 further comprising the steps of counting the number of performance enhancing and degrading events. ### Claim 4 (depends on 3) The method as defined in claim 3 further comprising the steps of: formulating a threshold, forming a difference between the numbers of performance enhancing and degrading events, comparing the difference to the threshold, and if the threshold is triggered, designating the cache data as a candidate for purging. ### Claim 5 (depends on 3) The method as defined in claim 3 further comprising the steps of: setting the difference to zero whenever a degrading event occurs, and incrementing the count whenever an enhancing event occurs. ### Claim 6 (depends on 4) The method as defined in claim 4 further comprising the steps of: after the threshold is triggered, starting a time out delay, wherein the time out delay must be completed before the cache data is purged. ### Claim 7 (depends on 1) The method as defined in claim 1 further comprising the step of evicting data from one cache level to a lower level wherein such eviction designates the cache data for purging. ### Claim 8 (depends on 6) The method as defined in claim 6, wherein the time out delay includes the step of counting miss events. ### Claim 9 (depends on 6) The method as defined in claim 6, wherein the time out includes the step of counting instructions executed. ### Claim 10 (depends on 6) The method as defined in claim 6, wherein the time out delay includes the step of counting clock cycles. ### Claim 11 (depends on 4) The method as defined in claim 4, wherein if the threshold i s not triggered, starting a fake time out delay, and, when the fake delay time out expires, if a write-hit occurs, resetting the count to zero; and if a read-dirty occurs, absent a write-hit, incrementing the count; but if before the fake delay has expired, if a read-dirty or victim occurs, stopping the fake time out. ### Claim 12 A system for adaptively determining cache data candidates for purging, wherein physical cache memory is associated with a local component of a local node in a modular multiprocessor system having a plurality of interconnected processors, I/O ports, and memory, the system comprising: means for determining system performance enhancing and degrading events occurring with respect to purging cache data, logic for first tracking performance enhancing events on the cache data, logic for second tracking performance degrading events on the cache data, means for assessing the impact on system performance by the first and second trackings, and in response thereto, if performance would be enhanced, means for designating the cache data for purging. ### Claim 13 (depends on 12) The system as defined in claim 12 wherein the means for determining system enhancing and degrading events includes: means for recognizing that: some read-dirties and certain references by remote processors after a purge are enhancing event, and that some writes to the data by the local processor that owns the data and some writes after the data has been purged are performance degrading events. ### Claim 14 (depends on 12) The system as defined in claim 12 further comprising logic for counting the number of performance enhancing and degrading events. ### Claim 15 (depends on 14) The system as defined in claim 14 further comprising: means for formulating a threshold, logic for forming a difference between the numbers of performance enhancing and degrading events, and a comparator for comparing the difference to the threshold, and if the threshold is triggered, and means for designating the cache data as a candidate for purging. ### Claim 16 (depends on 14) The system as defined in claim 14 further comprising: means for setting the difference to zero whenever a degrading event occurs, and means for incrementing the count whenever an enhancing event occurs. ### Claim 17 (depends on 15) The method as defined in claim 15 further comprising: after the threshold is triggered, means for starting a time out delay, wherein the time out delay must be completed before the cache data is purged. ### Claim 18 (depends on 12) The system as defined in claim 12 further comprising means for evicting data from one cache level to a lower level wherein such eviction designates the cache data for purging. ### Claim 19 (depends on 17) The system as defined in claim 17, wherein the time out delay includes the means for counting miss events. ### Claim 20 (depends on 17) The system as defined in claim 17, wherein the time out includes means for counting instructions executed. ### Claim 21 (depends on 17) The system as defined in claim 17, wherein the time out delay includes means for counting clock cycles. ### Claim 22 (depends on 15) The system as defined in claim 15 further comprising, wherein if the threshold is not triggered, means for starting a fake time out delay, and, when the fake delay time out expires, if a write-hit occurs, means for resetting the count to zero; and if a read-dirty occurs, absent a write-hit, means for incrementing the count; but if before the fake delay has expired, if a read-dirty or victim occurs, means for stopping the fake time out.