Charge pump power supply

A memory device including a charge pump circuit comprising:

• a first and second charge pump cascade, the first and second charge pump cascade comprising a plurality of charge pump stages;
• each of the plurality of charge pump stages comprising a transistor and a capacitor;
• and
• wherein the plurality of charge pump stages pump charge to an output node on both a rising edge and a falling edge of a system clock signal.

A charge pump comprising:

• a first and a second pump cascade coupled in parallel to an output node;
• the first and the second pump cascades comprising a plurality of pump stages coupled in series;
• wherein (2n)th pump stage of the first pump cascade is coupled to receive a first clock signal and (2n+1)th pump stage of the first pump cascade is coupled to receive a second clock signal, n being an integer greater than or equal to zero;
• wherein (2n)th pump stage of the second pump cascade is coupled to receive the second clock signal and (2n+1)th pump stage of the second pump cascade is coupled to receive the first clock signal, n being an integer greater than or equal to zero;
• and
• wherein the output node receives charge pumped by the first and the second pump cascades and provides an output supply voltage that is greater in magnitude than the power supply voltage.

A charge pump for generating a high voltage supply comprising:

• a first pump cascade comprising multiple charge pump stages, each charge pump stage in the first pump cascade being driven by a first plurality of clock signals;
• a second pump cascade comprising multiple charge pumps stages, each charge pump stage in the second pump cascade being driving by a second plurality of clock signals;
• a non-overlapping clock signal generator for generating the first and second plurality of clock signals in response to transitions in a system clock signal, each of the clock signals of the second plurality of clock signals having opposite phases to each of the clock signals of the first plurality of clock signals;
• and
• wherein final charge pump stages of the first and second pump cascades are coupled in parallel to provide the high voltage supply.

A memory device including a charge pump comprising:

• a first and second charge pump cascade, the first and second charge pump cascade comprising a plurality of charge pump stages;
• wherein each of the plurality of charge pump stages comprises a means for receiving charge and a means for storing charge;
• and
• means for driving an output node with charge stored in the plurality of charge pump stages on both a rising edge and a falling edge of a system clock signal.

A method for generating a voltage greater than a power supply voltage, comprising the steps of:

• providing the power supply voltage to a plurality of pump cascades comprising a plurality of pump stages;
• on a first edge of a system clock, storing charge from a power supply simultaneously in a first group of charge pump stages and pumping charge to an output node from a second group of charge pump stages;
• and
• on a second edge of the system clock, storing charge from the power supply simultaneously in the second group of charge pump stages and pumping charge to the output node from the first group of charge pump stages.

A method of operating a plurality of charge pump cascades, each charge pump cascades comprising a first and second group of charge pump stages, and wherein the charge pump cascades operate to pump electrical charge to an output supply node, the method comprising the steps of:

• in response to a leading edge of a system clock, pre-charging output nodes of the first group of charge pump stages to voltages present on respective input nodes in the first group of charge pump stages and subsequently boosting output nodes of the second group of charge pump stages to respective boosted voltages;
• in response to a trailing edge of the system clock, pre-charging output nodes in the second group of charge pump stages to voltages present on respective input nodes in the second group of charge pump stages and subsequently boosting output nodes in the first group of charge pump stages to respective boosted voltages;
• and
• providing charge in alteration from each of the charge pump cascades to the output supply node in response to both leading and trailing edges of the system clock until the output supply node reaches a predetermined voltage level.

A non-overlapping clock signal generator comprising:

• a system clock input node;
• a clock input stage;
• a latch coupled to the clock input stage having intermediate latch outputs and complementary latch outputs;
• clock output driving stages coupled to the complementary latch outputs and having non-overlapping clock signal outputs;
• and
• and equalization stage coupled between the clock output driving stages and receiving as inputs the intermediate latch outputs.