Design method for semiconductor integrated circuit device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorKazuyoshi Takemura
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Abstract
A design method for a semiconductor integrated circuit device enabling flexible selection of IPs while securing the functions of a system is provided. The design method of the present invention includes the steps of: (a) storing a plurality of IPs having the same function in a memory for each of a plurality of functions; (b) constructing a function group structure for satisfying a certain specification; and (c) selecting and retrieving one IP from the plurality of IPs having the same function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure.
Claims18
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of IPs having the same function in a memory for each of a plurality of functions;
- (b) constructing a function group structure for satisfying a certain specification;
- and
- (c) selecting and retrieving one IP from the plurality of IPs having the same function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure.
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of IPs each having a function in a memory;
- (b) constructing a function group structure for satisfying a certain specification;
- (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure;
- (d) expanding the IP hierarchically into functional blocks;
- and
- (e) mapping each of the functional blocks obtained by the hierarchical expansion to a HW model and a SW model of architecture models in a database.
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of HW models in a memory as architecture models;
- and
- (b) retrieving architecture models from the memory to construct an architecture group structure satisfying a certain specification,
- wherein in the step (b), the architecture group structure is constructed so that the architecture group structure includes a plurality of bus models and a plurality of bus bridge models for connecting the bus models.
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of HW models in a memory as architecture models;
- (b) retrieving architecture models from the memory to construct an architecture group structure satisfying a certain specification,
- (c) constructing a function group structure for satisfying the certain specification;
- (d) providing test benches on input and output sides of the function group structure;
- and
- (e) mapping functions in the function group structure and the test benches to the models in the architecture group structure.
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of IPs each having a function in a memory;
- (b) constructing a function group structure for satisfying a certain specification;
- (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure, and substituting the IP for the function in the function group structure;
- (d) expanding the IP hierarchically to functional blocks;
- (e) mapping each functional block obtained by the hierarchical expansion to a model in an architecture group structure;
- and
- (f) preparing an inter-block connection table describing a path from the functional block to another functional block receiving an output from the functional block as an intermodel path in the architecture models.
A design method for a semiconductor integrated circuit device comprising the steps of:
- (a) storing a plurality of IPs each having a function in a memory;
- (b) constructing a function group structure for satisfying a certain specification;
- (c) selecting and retrieving an IP having a function from the memory for each function in the function group structure and substituting the IP for the function in the function group structure;
- (e) mapping each function in the function group structure to a model in architecture models in a database;
- (f) setting priority of the model for access to a bus;
- and
- (g) performing static performance analysis for the function group structure in the state where the respective functions in the function group structure have been mapped to the models,
- wherein in the static performance analysis, the power consumption of the function group structure is calculated using the priority of each model for access to a bus in the architecture group structure instead of the number of toggles.
Dependencies are inferred from the claim text.