Semiconductor integrated circuit including a test facilitation circuit for functional blocks intellectual properties and automatic insertion method of the same test facilitation circuit
AssigneeKabushiki Kaisha Toshiba
InventorYasuyuki Nozuyama
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Abstract
This invention provides a semiconductor integrated circuit in which test facilitation technology (design for testability) of system on a chip (SOC) constructed of functional blocks or intellectual properties (IPs) is improved. This semiconductor integrated circuit takes out a test result of the functional block out of the SOC through a test result storage circuit which signature-compresses the test result.
Claims20
A semiconductor integrated circuit including plural functional blocks connected to each other, the semiconductor integrated circuit comprising:
- a selection circuit which selects any one of plural inputs;
- a bi-directional selection circuit which exchanges data bi-directionally;
- the functional block including an input terminal connected to an output terminal of other functional block and an input terminal of the semiconductor integrated circuit through the selection circuit, and a bi-directional terminal connected to the bi-directional terminal of the other functional block and a bi-directional terminal of the semiconductor integrated circuit through the bi-directional selection circuit;
- and
- a test result storage circuit which functions as a test facilitation circuit such that it is connected to an output terminal of the functional block, receives test results of plural bits (n) in parallel from the functional block, signature-compresses the test results, and outputs the signature-compressed data from an output terminal of the semiconductor integrated circuit in the unit of m (m<n) bits which is smaller than the plural (n) bits.
An automatic insertion method of a test facilitation circuit for inserting the test facilitation circuit into a semiconductor integrated circuit constructed by connecting plural functional blocks to each other, the automatic insertion method comprising:
- inputting relating data of the semiconductor integrated circuit;
- wherein the relating data include input/output terminals of the semiconductor integrated circuit, a input/output terminals available for test for the functional blocks and a net data indicating connection inside the semiconductor integrated circuit between input/output terminals of the semiconductor integrated circuit and input/output terminals of the functional blocks for realizing the function of the semiconductor integrated circuit and test patterns which confirms operation of the semiconductor integrated circuit, and relating data of the functional blocks including the input/output terminals of the functional blocks;
- information describing operation which realizes function of the functional blocks, kind of the test facilitation method for testing whether or not there is a fault and test patterns prepared according to the method;
- inserting a test result storage circuit which functions as the test facilitation circuit for the functional blocks which are test objects into the semiconductor integrated circuit based on the inputting;
- and
- outputting a relating information after a insertion of the test facilitation circuit to the semiconductor integrated circuit, wherein the relating information includes a net data of the semiconductor integrated circuit in which the test facilitation circuit is inserted, and test patterns obtained by converting test patterns of the functional blocks for being used in the semiconductor integrated circuit in which the test facilitation circuit is inserted.
Dependencies are inferred from the claim text.