Method of generating a pattern for testing a logic circuit and apparatus for doing the same
AssigneeNEC Electronics Corporation
InventorHirofumi Yonetoku
Life of this patent
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Abstract
A method of generating a pattern for testing a logic circuit, includes the steps of (a) judging whether generation of a test pattern is to be finished, (b) selecting a fault for which the test pattern is to be generated, if generation of the test pattern is judged to be continued in the step (a), (c) attempting generating at least one test pattern necessary for detecting the fault selected in the step (b), and (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of the at least one test pattern, and re-activating the thus found test pattern, if the at least one test pattern is generated in the step (c).
Claims83
A method of generating a pattern for testing a logic circuit, comprising the steps of:
- (a) judging whether generation of a test pattern is to be finished;
- (b) selecting a fault for which said test pattern is to be generated, if generation of said test pattern is judged to be continued in said step (a);
- (c) attempting generating at least one test pattern necessary for detecting said fault selected in said step (b);
- and
- (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activating the thus found test pattern, if said at least one test pattern is generated in said step (c).
A method of generating a pattern for testing a logic circuit, comprising the steps of:
- (a) judging whether generation of a test pattern is to be finished;
- (b) receiving at least one test pattern from an external memory, if generation of said test pattern is judged to be continued in said step (a);
- (c) checking whether a fault is detected in all test patterns having been received in said step (b), if a circuit to be tested is a combinational circuit;
- and
- (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activating the thus found test pattern, if said fault is detected in said step (c).
A method of generating a pattern for testing a logic circuit, comprising the steps of:
- (a) judging whether generation of a test pattern is to be finished;
- (b) receiving at least one test pattern from an external memory, if generation of said test pattern is judged to be continued in said step (a);
- (c) generating at least one test pattern, based on a test pattern which detects a fault, if a circuit to be tested is a sequential circuit;
- and
- (d) carrying out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activating the thus found test pattern.
An apparatus for generating a pattern for testing a logic circuit, comprising:
- (a) a judge which judges whether generation of a test pattern is to be finished;
- (b) a selector which selects a fault for which said test pattern is to be generated, if generation of said test pattern is judged to be continued in said step (a);
- (c) a pattern generator which attempts generating at least one test pattern necessary for detecting said fault selected by said selector;
- and
- (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activates the thus found test pattern, if said at least one test pattern is generated by said pattern generator.
An apparatus for generating a pattern for testing a logic circuit, comprising:
- (a) a judge which judges whether generation of a test pattern is to be finished;
- (b) a receiver which receives at least one test pattern from an external memory, if generation of said test pattern is judged to be continued by said judge;
- (c) a checker which checks whether a fault is detected in all test patterns having been received by said receiver, if a circuit to be tested is a combinational circuit;
- and
- (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activates the thus found test pattern, if said fault is detected by said checker.
An apparatus for generating a pattern for testing a logic circuit, comprising:
- (a) a judge which judges whether generation of a test pattern is to be finished;
- (b) a receiver which receives at least one test pattern from an external memory, if generation of said test pattern is judged to be continued by said judge;
- (c) a pattern generator which generates at least one test pattern, based on a test pattern which detects a fault, if a circuit to be tested is a sequential circuit;
- and
- (d) a simulator which carries out fault simulation to find a test pattern by which undetected faults are detected most, among copies of said at least one test pattern, and re-activates the thus found test pattern.
Dependencies are inferred from the claim text.