Automatic detection of connectivity between an emulator and a target device
AssigneeTexas Instruments Incorporated
InventorGary L. Swoboda
Life of this patent
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Abstract
Connectivity between an emulation controller and a plurality of target devices can be automatically detected. After the target devices (Chip1, ChipN) and the emulation controller (12) tri-state respective terminals thereof, one of the target devices drives a predetermined logic level on each of the aforementioned terminals thereof in sequence, while maintaining the remainder of the aforementioned terminals thereof tri-stated. These driving (33) and maintaining (31) operations are thereafter performed by each of the remaining target devices in sequence. During each driving step, all of the target devices and the emulation controller read logic levels at their aforementioned terminals (34, 43).
Claims17
A method of automatically detecting connectivity between an emulation controller and a plurality of target devices, comprising:
- each target device tri-stating terminals thereof;
- the emulation controller tri-stating terminals thereof;
- one of the target devices driving a predetermined logic level on each of said terminals thereof in sequence, while maintaining the remainder of said terminals thereof tri-stated;
- each of the remaining target devices performing said driving and maintaining step in sequence after said one target device;
- and
- each of the target devices reading logic levels at said terminals thereof during each said driving step, and the emulation controller reading logic levels at said terminals thereof during each said driving step.
An integrated circuit device capable of supporting automatic detection of connectivity with an external emulation controller, comprising:
- a plurality of terminals for signaling with external devices;
- terminal control circuitry coupled to said terminals for selectively tri-stating and driving a predetermined logic level on said terminals;
- and
- a control register coupled to said terminal control circuitry for controlling said terminal control circuitry such that said predetermined logic level is driven on each of said terminals in sequence while the remainder of said terminals are tri-stated.
Dependencies are inferred from the claim text.