US 2002/0059536 A1 · Clock controlling method and clock control circuit

A clock control circuit comprising:

a delay circuit sequence including a plurality number of cascaded stages of delay circuit units, each made up of a first circuit receiving an input signal to output said input signal with a first delay time and a second circuit receiving an output signal from said first circuit to output said signal with a second delay time;
a phase difference detection circuit receiving an input clock fed to said delay circuit sequence and an output clock output from said delay circuit sequence to detect a time difference between a clock period of said input clock and a delay time of said delay circuit sequence as a phase difference of said received two clocks;
and
a plurality of third circuits, each receiving an output signal of said first circuit of each of said delay circuit units to delay and output transition edge of said output signal of said first circuit with respective different delay time, depending on a stage number of said delay circuit unit to which belongs said first circuit in said delay circuit sequence, in terms of time obtained on equally dividing said phase difference by the number of said delay circuit units in said delay circuit sequence, as a unit;
wherein said third circuits output a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock by the number of said delay circuit units in said delay circuit sequence.

2 more elements

A clock control circuit comprising:

a delay circuit sequence comprised of a plural number (N) of cascaded stages of delay circuit units, each made up of a first delay circuit with a first delay time t1 and a second delay circuit for delaying and outputting rise or fall transition edge of an output signal of said first delay circuit with a second delay time t2;
to said delay circuit sequence an input clock with a clock period tCK being entered from a stage number 1 delay circuit unit;
a phase difference detection circuit receiving an output clock output from the last stage delay circuit unit of said delay circuit sequence and an input clock entered to said delay circuit sequence to detect from said two clocks a phase difference T corresponding to a time difference between a delay time of said delay circuit sequence and the period tCK of said input clock (T=N×(t1+t2−tCK);
(N−1) third delay circuits receiving respectively an output signal of a first delay circuit of from stage number 1 to stage number (N−1) said delay circuit units;
a number n said third delay circuit, where n is a positive integer of from 1 toN−1, delaying transition edge of an output signal of said first delay circuit of a corresponding stage number n delay circuit unit, based on the phase difference T as detected by said phase difference detection circuit, by time t2−n×T/N which is corresponding to said second delay time t2 less a delay time n×T/N corresponding to the phase T/N, obtained on equally dividing the phase difference T by the number N of the delay circuit units multiplied by the number of stages n in the delay circuit sequence of said delay circuit units corresponding to said third delay circuit, and outputting the delayed signal;
the number n said third delay circuit, where n is an integer from 1 to N−1, outputting a signal which makes a rise or fall transition at a timing delayed as from a start time point of a clock cycle of said input clock by time n×(t1+t2−T/N)=n×tCK/N;
and
a synthesis circuit for generating a frequency multiplied clock signal of a clock period obtained on equal division of the clock period tCK of said input clock based from said input clock and output signals output from number 1 to number (N−1) said third delay circuits.

5 more elements

A clock control circuit comprising:

a delay circuit sequence including a plurality number of cascaded (N) stages of delay circuit units each made up of a first delay circuit with a first delay time t1 and a second delay circuit for delaying and outputting the rise or fall transition edge of an output signal of said first delay circuit with a second delay time t2, said delay circuit sequence receiving an input clock with a period tCK and outputting the received clock after a time delay of ×(t1+t2);
said second delay circuit comprised of a first interior division circuit comprising:
a first switch for turning on a charging path of said first capacitor in said second delay circuit when an output signal of said first delay circuit input to said second delay circuit is of a second value;
N parallel-connected second switches for turning on a discharge path for discharging the electric charge accumulated in said first capacitor when the output signal of said first delay circuit is of a first value;
and
a first buffer circuit for outputting a logic value corresponding to the magnitude relation between said terminal voltage of said first capacitor and a threshold value;
there being provided a phase difference detection circuit for detecting a phase difference T (T=N×(t=1+t2)−tCK) between an output clock output from the last stage delay circuit unit of said delay circuit sequence and an input clock of the next clock cycle associated with said output clock to output a signal in an activated state for a time corresponding to said phase difference;
with the time period tCK/N corresponding to N equal division of one clock period tCK of said input clock being represented as t1+t2−T/N;
there being provided number 1 to numberN−1 second interior division circuits in association with said first delay circuits of the stage number 1 to stage number N delay circuit units;
a number n second interior division circuit, receiving an output signal of the first delay circuit of a number n first delay circuit, n being a positive integer from 1 o N−1, comprising:
a third switch for controlling on and off of a charging path of a second capacitor in said second interior division circuit;
a plurality of parallel-connected fourth switches for controlling on and off of a discharge path for discharging the electric charge accumulated in said second capacitor;
and
a second buffer circuit for outputting a logical value corresponding to the magnitude relation between said terminal voltage of said second capacitor and a threshold value;
n of said plural fourth switches being turned on during the active period of an output signal of said phase difference detection circuit to partially discharge the electric charge accumulated in said second capacitor, N of said plural fourth switches being turned on to discharge said partially discharged second capacitor as from a time point the output signal of the number n first delay circuit is changed to a first value,
said second buffer circuit outputting an output signal which makes a transition to a high or low level at a timing of a delay time t2−n×T/N as from the rise or fall transition timing (N−1)×(t1+t2)+t1 of the number n first delay circuit, said output signal having transition timing of n(t1+t2−T/N)=n×tCK/N as from the clock cycle start time point which is the transition timing of said input clock;
the number 1 to number N−1 second interior division circuit outputting (N−1) clocks which make transition at a time interval tCK/N corresponding to N equal division of one clock period tCK of said input clock.

14 more elements

A signal generating circuit comprising:

a delay circuit sequence including a plurality of cascaded stages of delay circuit units each made up of a first circuit outputting an input signal with a first delay time and a second circuit outputting an output signal of said first circuit with a second delay time;
a phase difference detection circuit receiving an input clock input to said delay circuit sequence and an output clock output from said delay circuit sequence with a delay to detect the time difference between the period of said input signal and the delay time of said delay circuit sequence as a phase difference of said two input clock;
and
a plurality of third circuits, each receiving an output signal of said first circuit of each of said delay circuit units for outputting transition edge of the output signal of said first circuit with respective different delay time, depending on the stage number of said delay circuit in said delay circuit sequence to which belongs said first circuit, in terms of the time obtained on equally dividing said phase difference with the number of said delay circuit units in said delay circuit sequence, as a unit;
said third circuits outputting a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock with the number of said delay circuit units in said cascaded connection of said delay circuit sequence.

2 more elements

A clock control circuit comprising

a delay circuit sequence including a plurality of cascaded stages of delay circuit units each made up of a first circuit for outputting an input signal with a first delay time;
a phase difference detection circuit receiving an input clock input to said delay circuit sequence and an output clock output from said delay circuit sequence to detect the time difference between the clock period of said input clock and the delay time of said delay circuit sequence as a phase difference of said two input clock;
and
a plurality of second circuits fed with an output signal of a plurality of said first circuits for outputting transition edges of the output signals of said first circuit with respective different delay time, depending on the stage number of said delay circuit in said delay circuit sequence, in terms of the time obtained on equally dividing said phase difference with the number of said delay circuit units in said delay circuit sequence, as a unit;
said second circuits outputting a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock with the number of said delay circuit units in said delay circuit sequence.

2 more elements

A clock control circuit comprising:

a delay circuit sequence comprised of a plural number (N) of cascaded stages of first delay circuits, each with delay time t1;
said delay circuit sequence being fed with input clock of a period tCK from a stage number 1 first delay circuit;
a phase difference detection circuit for detecting a phase difference T (T=tCK−N×t1) corresponding to the time difference between the delay time of said delay circuit sequence and the clock period tCK of said input clock, from an output clock output from the last stage first delay circuit of said delay circuit sequence and an input clock input to said delay circuit sequence;
N second delays circuits fed respectively with outputs of number 1 to number N first delay circuits;
the number n second delay circuit, n being a positive integer from 1 to N, delaying transition edge of an output signal of the corresponding stage number n first delay circuit, based on a phase difference T detected by the phase difference detection circuit, by a time corresponding to the delay time proper to said plural second delay circuits tpd less (N−n)×T/N corresponding to a product of the phase T/N corresponding to the phase difference T divided equally by the total number of first delay circuits with the difference between N and the number of stages n of said first delay circuits in said delay circuit sequence;
the number n second delay circuit, n being a positive integer from 1 to N, outputting signals making rise or fall transition with a timing delayed by
n×t1+tpd−(1−n/N)×T
as from the start time point of the clock cycle of said input clock;
multi-phase clocks with a time interval of t1+T/N being generated from an output signal of each of the number 1 to number N second delay circuits.

6 more elements

A clock control circuit comprising:

a delay circuit sequence including a plural number of cascaded stages (N stages) of delay circuits with a delay time t1, said delay circuit sequence receiving an input clock with a clock period of tCK and outputting the clock with a time delay of N×t1;
a phase difference detection circuit receiving said input clock and an output clock of the last stage first delay circuit of said delay circuit sequence to detect a phase difference T (T=tCK−N×t1) between said output clock and the input clock of the next cycle associated with said output clock to output an activated output signal during the time corresponding to said phase difference T;
with the period corresponding to N equal division of one clock period tCK of said input clock being given as t1+T/N;
and
number 1 to number N interior division circuits associated with the stage number 1 to stage number N first delay circuits;
the number n interior division circuit, receiving an output signal of the number n first delay circuit, n being a positive integer from 1 toN−1, including:
a first switch for controlling on and off of the charging path of a capacitor in said interior division circuit;
a plurality of parallel-connected second switches for controlling on and off of a discharge path for discharging the electric charge accumulated in said capacitor;
and
a buffer circuit for outputting a logic value corresponding to the magnitude relation between said terminal voltage of said capacitor and a threshold value;
wherein n of said plural switches is turned on during an activated period of the output signal of said phase difference detection circuit to partially discharge the electric charge of said capacitor, N of said plural second switches is turned on as from a time point the output signal of the number n first delay circuit is changed to a first value to discharge the capacitor, and said buffer circuit outputs an output signal which makes rise or fall transition with a delay time from a rise or fall transition timing of an output signal of the number n first delay circuit or n×t1, said delay time corresponding to a time proper to the interior division circuit subtracted by (N-n)X T/N;
and
wherein the number 1 to number N said interior division circuits output N multi-phase clocks which make transition with an equal time interval t1+T/N.

10 more elements

A clock controlling method comprising the steps of:

entering an input clock to a delay circuit sequence including a plurality number of cascaded stages of delay circuit units each made up of a first circuit for outputting an input signal with a first delay time and a second circuit for outputting an output signal of said first circuit with a second delay time;
detecting, by a phase difference detection circuit, a phase difference between a clock pulse of the clock cycle next to the input clock fed to said delay circuit sequence and a clock pulse output from the last state delay circuit unit of the delay circuit sequence, that is a difference between the delay time of the delay circuit sequence and the clock period of input clock;
and
outputting, from a plurality of third circuits which receives output signals of the first circuits of said plural delay circuit units, transition edges of the output signals of said first circuits with respective different delay time, depending on a stage number of said delay circuit unit to which belongs said first circuit in said delay circuit sequence, in terms of time obtained on equally dividing said phase difference by the number of said delay circuit units in said delay circuit sequence, as a unit;
wherein said third circuits outputs a plurality of output signals which make transition at a time interval corresponding to equal division of the clock period of said input clock with the number of said delay circuit units in said delay circuit sequence.

2 more elements

A clock controlling method for outputting a frequency multiplied clock signal synchronized with an input clock, comprising the steps of:

entering an input clock of a clock period tCK to a delay circuit sequence comprised of N cascaded stages of first delay circuits with a delay time t1 and second delay circuits for delaying the rising or falling edges of the output signal of the first delay circuit with a delay time t2, and outputting the delayed signal;
detecting, by a phase difference detection circuit, a phase difference T (T=N×(t1+t2)−tCK) between an output clock output from the last stage first delay circuit of the delay circuit sequence and the input clock of the next cycle input clock to the input clock associated with said output clock;
1 to N−1 third delay circuits in association with the number 1 to number N first delay circuits being provided, said third delay circuits being fed with outputs of said first delay circuits of the stage number 1 to stage number N−1 delay circuit units;
the number n said third delay circuit, n being an integer from 1 to N−1, outputting, based on the phase difference T as detected by said phase difference detection circuit, transition edge of the output signal of the associated stage number n first delay circuit, with a delay corresponding to the second delay time t2 less the product of the number of sages n in the delay circuit sequence of the delay circuit units associated with the third delay circuits with the phase T/N corresponding to division of the phase difference T by the number of the delay circuit units, or t2−n×T/N;
the number n said third delay circuit, n being a positive integer from 1 to N, outputting a signal making rise or fall transition with a timing delayed by
n×(t1+t2−T/N)
from the start time point of the clock cycle of the input clock;
and
generating a frequency multiplied clock signal of a clock period corresponding to equal division of a clock period of the input clock being by synthesizing the input clock and the outputs of the number 1 to number N−1 third delay circuits.

6 more elements

A clock controlling method for outputting a frequency multiplied clock signal synchronized with an input clock, comprising the steps of:

entering an input clock of a clock period tCK to a delay circuit sequence comprised of N cascaded stages of first delay circuits with a delay time t1, said delay circuit sequence being fed with input clock with a period of tCK;
detecting, by a phase difference detection circuit, a phase difference T (T=tCK−N×t1) between an output clock output from the last stage first delay circuit of the delay circuit sequence and the input clock of the next cycle input clock to the input clock associated with said output clock;
N second delay circuits in association with the number 1 to number N first delay circuits being provided, said second delay circuits being fed with outputs of said first delay circuits;
the number n second delay circuit, n being an integer from 1 to N, outputting, based on the phase difference T as detected by said phase difference detection circuit, the transition edges of the output signal of the associated stage number n first delay circuit, with a delay corresponding to the delay time tpd proper to said plural second delay circuits less the time prescribed by the difference between the total number N of the first delay circuits and the number of stages n in the delay circuit sequence of said first delay circuits, or (N−n)×T/N;
the number n second delay circuit, n being a positive integer from 1 to N, outputting a signal making rise or fall transition with a timing delayed by
n×t1+tpd−(1−n/N)×T
from the start time point of the clock cycle of the input clock;
and
generating multi-phase clocks with a time interval of t1+T/N from output signals of the number 1 to number N second delay circuits.

6 more elements

A clock controlling circuit comprising:

a first delay circuit sequence including plural cascaded stages of delay circuits;
a second delay circuit sequence including plural cascaded stages of delay circuits;
an input clock received by the stage 1 delay circuit of said first delay circuit sequence being output from the last stage delay circuit of the first delay circuit sequence after propagation through said first delay circuit sequence to be input to the stage 1 delay circuit of said second delay circuit sequence for propagation through said second delay circuit sequence;
a plurality of interior division circuits arranged in juxtaposition to one another in association with respective stages of the delay circuits of said first and second delay circuit sequences for outputting output signals with a delay time prescribed by the time corresponding to division of the phase difference between two input signals with a preset interior division ratio, the number 1 interior division circuit of said juxtaposed plural interior division circuits being fed with an input clock output by said first delay circuit sequence and fed to the stage number 1 delay circuit of the second delay circuit sequence and the next cycle input clock;
the number n+1 interior division circuit, n being an optional integer such that n+1 is not less than 2 and not larger than the stage number of the last stage delay circuit of said first delay circuit sequence, being fed with an output signal of the stage number n delay circuit of the second delay circuit sequence associated with the interior division circuit and with an output signal of the stage number n delay circuit of said first delay circuit sequence fed with the input clock of the next cycle;
the interior division ratio of plural interior division circuits being set so as to be larger every unit value in association with the order of said interior division circuits;, such that, if, with the input clock period tCK<the number of stages of the last stage delay circuit of said first delay circuit sequence being n and the delay time of each delay circuit being td,
T=tCK−N×td,
the interior division ratio of said plural interior division circuits is set such as to increase the respective delay time every preset unit T/N, with the phase difference between output signals of two neighboring interior division circuits being tCK/N, with the phase difference between the output signal of the number 1 interior division circuit and the number (N+1) interior division circuit being 2π.

5 more elements

A clock control circuit comprising

a first delay circuit sequence including 2N cascaded stages of first delay circuit sequences, with a non-inverting-phase clock being input at a stage number 1 delay circuit of said first delay circuit sequence for propagation through said first delay circuit sequence, where N is an integer not less than 1;
a second delay circuit sequence including 2N cascaded stages of second delay circuit sequences, with an inverting phase clock being input at a stage number 1 delay circuit of said second delay circuit sequence for propagation through said second delay circuit sequence, where N is an integer not less than 1;
first and second groups of interior division circuits, each group including (N+1) interior division circuits for outputting an output signal of a delay time prescribed by the time obtained on dividing a phase difference of two input signals with a preset interior division ratio;
the interior division ratio of said (N+1) interior division circuits being set to respective different values in each group;
the number 1 interior division circuit of the first group of the interior division circuits being fed with an output signal of the stage number N delay circuit of said second delay circuit sequence and with a forward phase clock of the next cycle;
the number i interior division circuit of the first group of the interior division circuits, i being a number from 2 to N+1, being fed with an output signal of the number (N+i−1) delay circuit of said second delay circuit sequence and with an output signal of said delay circuit of the (i−1) stage number delay circuit of said first delay circuit sequence fed with forward phase clocks of the next cycle;
the number 1 to number (N+1) interior division circuit of said first group of the interior division circuits outputting multi-phase clocks of a phase difference corresponding to N equal division of one half of the period of the input clock (phase π);
the number 1 interior division circuit of the second group of the interior division circuits being fed with an output signal of the stage number N delay circuit of said first delay circuit sequence and with reverse-phase clocks of the next cycle;
the number i interior division circuit of the second group of the delay circuit sequence, i being an integer from 2 to N+1, being fed with an output signal of the stage number (N+i−1) delay circuit of said first delay circuit sequence and with an output signal of the stage number (i−1) delay circuit of the second delay circuit sequence fed with a reverse phase clock of the next cycle;
the number 1 to number (N+1) interior division circuit of the second group of the interior division circuits outputting multi-phase clocks of a phase difference corresponding to N equal division of one half the clock period (phase π) of said input clock with a phase shift of π from an output signal of the number 1 to number (N+1) interior division circuits of the first group of the interior division circuits.

7 more elements

A clock control circuit comprising:

first and second delay circuit sequences comprised of N cascaded stages of delay circuits, N being an integer not less than 1;
an input clock being fed to said delay circuit of the number 1 delay circuit of the first delay circuit sequence so as to be propagated through said first delay circuit sequence;
a selection circuit receiving an output signal of each delay circuit of said first delay circuit sequence to select one delay circuit output depending on a multiplication value K as specified by an input multiplication value determining signal, K being an integer not less than 1 and not larger than N;
an output signal of said selection circuit being fed to the stage number 1 delay circuit of said second delay circuit sequence so as to be propagated through said second delay circuit sequence;
and
at least N interior division circuits arranged in juxtaposition for outputting an output signal of a delay time prescribed by the time corresponding to division of a phase difference of two input signals with a preset interior division ratio;
the interior division ratio of said interior division circuits differing from one another and being prescribed by the multiplication value K specified by said multiplication value determining signal;
the number 1 interior division circuit being fed with an output signal of said selection circuit and with an input clock of the next cycle;
the number i interior division circuit, i being an integer from 2 to N, being fed with an output signal of the stage number (i−1) delay circuit of said second delay circuit sequence and with an output signal of the stage number (i−1) delay circuit of the first delay circuit sequence of the next cycle clock;
the number i to number K interior division circuit outputting multi-phase clocks of a phase difference corresponding to K equal division of said input clock;
said multiplication value K being varied by said multiplication value determining signal.

8 more elements

A clock controlling method comprising the steps of:

entering a non-inverting phase clock to a stage number 1 delay circuit of a first delay circuit sequence so as to be propagated through said first delay circuit sequence comprised of 2N cascaded stages of delay circuits, N being an integer not less than 1;
entering an-inverting phase clock to a stage number 1 delay circuit of a second delay circuit sequence so as to be propagated through said second delay circuit sequence comprised of 2N cascaded stages of delay circuits, N being an integer not less than 1;
the (N+1) interior division circuits making up each of first and second groups of interior division circuits, adapted for outputting output signals of delay time prescribed by time corresponding to division of a phase difference of two input signals by a preset interior division ratio, setting the interior division ratio of (N+1) interior division circuits to respective different values;
the number 1 interior division circuit of said first group of interior division circuits being fed with an output signal of a stage number N delay circuit and a forward phase clock of the next cycle in the number 1 interior division circuit of said first group of the interior division circuits;
the number i interior division circuit of said first group of interior division circuits, i being an integer from 2 to N+1, being fed with an output signal of the stage number (N+i−1) delay circuit of said second delay circuit sequence in the number i interior division circuit of the first group of interior division circuits, i being an integer from 2 to N+1, and an output signal of the stage number (i−1) delay circuit of said first delay circuit sequence fed with the forward phase clocks of the next cycle;
the number 1 to number (N+1) interior division circuits of said first group of interior division circuits outputting multi-phase clocks of a phase difference corresponding to N equal division of one half of the period of said input clock (phase of π);
the number 1 interior division circuit of said second group of the interior division circuits being fed with an output signal of a stage number N delay circuit and a reverse phase clock of the next cycle;
the number i interior division circuit of the second group of interior division circuits being fed with an output signal of the stage number (N+i−1) delay circuit of said first delay circuit sequence, i being an integer from 2 to N+1, and with an output signal of the stage number (i−1) delay circuit of said second delay circuit sequence fed with the forward phase clocks of the next cycle;
and
the number 1 to number (N+1) interior division circuits of said second group of the interior division circuits outputting multi-phase clocks of a phase difference corresponding to N equal division of one half of the period of the input clock (phase of π), with a phase shift π from the output signals of the number 1 to number (N+1) interior division circuits of said first group of the interior division circuits.

7 more elements

A clock controlling method comprising:

entering an input clock to a stage number 1 delay circuit of a first delay circuit sequence comprised of N cascaded stages of delay circuits, N being an integer not less than 1;
a selection circuit receiving an output signal of each delay circuit of said first delay circuit sequence and selecting one output depending on a multiplication value K, as specified by a multiplication value determining signal, K being an integer not less than 1 and not larger than N,
feeding an output signal of said selection circuit to a stage number 1 delay circuit of said second delay circuit sequence comprised of N cascaded delay circuits, N being an integer not less than 1;
juxtaposing at least N interior division circuits outputting an output signal of a delay time prescribed by time corresponding to division of a phase difference of two input signals with a preset interior division ratio, a number i interior division circuit of the interior division circuits, having respective different values of the interior division ratio and prescribed by the multiplication value, as specified by the multiplication value determining signal, being fed with an output signal of said selection circuit and with an input clock of the next cycle;
a number i interior division circuit, i being an integer from 2 to N, being fed with an output signal of an (i−1) stage number delay circuit of said second delay circuit sequence and with an output signal of an (i−1) stage number delay circuit of said first delay circuit sequence of the clock of the next cycle;
and
number 1 to number K interior division circuits outputting multi-phase clocks having a phase difference corresponding to K equal division of the period of said input clock.

4 more elements

Clock controlling method and clock control circuit

Life of this patent

Clock controlling method and clock control circuit

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Abstract

Claims58