Microprocessor architecture capable of supporting multiple heterogeneous processors

A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:

• means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus;
• means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read request from said master;
• means for providing an intervention signal (ITV) to said master when one of said slaves has modified the data associated with said address placed on said MAU address bus by said master;
• means responsive to said ITV signal for causing said master to disregard the data received from said address associated with said read request;
• and
• means for writing said modified data in said slave to said address associated with said read request.

A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:

• means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus;
• means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a write request from said master;
• and
• means for causing each of said slaves having data in a cache from said address associated with said write request to invalidate said data in said cache.

A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:

• means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus;
• means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master;
• means for providing an intervention signal (ITV) to said master when one of said slaves has modified the data from said address associated with said read-with-intent-to-modify request from said master;
• means responsive to said ITV signal for causing said master to disregard the data received from said address associated with said read-with-intent-to-modify request;
• and
• means for writing said modified data in said slave to said address associated with said read-with-intent-to-modify request.

A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:

• means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus;
• means enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master;
• and
• means for causing each of said slaves having unmodified data from said address associated with said write request to invalidate said data.

A multiprocessor architecture capable of supporting multiple processors wherein one of said processors is a master and all other processors are slaves comprising:

• means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus;
• means for comparing successive addresses appearing on the MAU address bus;
• and
• means responsive to said comparing means for continuously asserting a row address strobe (RAS) so long as said successive addresses appearing on said MAU address bus comprise the same row address.

A multiprocessor architecture capable of supporting multiple processors comprising:

• means located in each of said processors for generating a memory refresh request after a predetermined number of machine cycles;
• means located in each of said processors for keeping track of the number of times said request is denied since the last time it was granted;
• and
• means located in each of said processors for increasing the priority of said memory refresh request when said number reaches a predetermined magnitude, such that said memory is refreshed within a predetermined time period.

A method of transferring data in a multiprocessor architecture capable of supporting a plurality of microprocessors, each of said microprocessors having a data (D) cache, an instruction (I) cache, a memory port, an input/output unit (IOU) and a memory control unit (MCU), said MCU having a switch network, a D-cache interface circuit, means for coupling said D-cache interface circuit between said D-cache and said switch network, an I-cache interface circuit, means for coupling said I-cache interface circuit between said I-cache and said switch network, an I/O interface circuit, means for coupling said I/o interface circuit between said IOU and said switch network, a memory port interface circuit, means for coupling said memory port interface circuit between said memory port and said switch network, switch arbitration means for arbitrating for said switch network and port arbitration means for arbitrating for said memory port, comprising the steps of:

• transferring to said port arbitration means a request to transfer data between one of said D-cache, said I-cache and said IOU and said memory port through said switch network and said port interface circuit;
• transferring a port available signal from said port arbitration means to said switch arbitration means when said port interface circuit is free to process said request;
• and
• transferring a switch available signal from said switch arbitration means to the source of said request and to said port arbitration means when said switch network is free to process said request whereby data is enabled to be transferred between said one of said D-cache, said I-cache and IOU and said memory port.

A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:

• enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read request from said master;
• providing an intervention signal (ITV) to said master when one of said slaves has modified the data associated with said address placed on said MAU address bus by said master;
• causing said master to disregard the data received from said address associated with said read request in response to said ITV signal;
• and
• writing said modified data in said slave to said address associated with said read request.

A method of transferring data in a multiprocessor architecture capable of supporting multiple processors having a means for coupling each of said processors to a memory array unit (MAU) via an MAU system bus, said MAU system bus including an MAU address bus, an MAU data bus and an MAU control signal bus and wherein one of said processors is a master and all other processors are slaves comprising the steps of:

• enabling each of said slaves to snoop for an address placed on said MAU address bus in association with a read-with-intent-to-modify request from said master;
• providing an intervention signal (ITV) to said master when one of said slaves has modified the data from said address associated with said read-with-intent-to-modify request from said master;
• causing said master to disregard the data received from said address associated with said read-with-intent-to-modify request in response to said ITV signal;
• and
• writing said modified data in said slave to said address associated with said read-with-intent-to-modify request.

A method of transferring data in a multiprocessor architecture capable of supporting multiple processors comprising the steps of,.

• providing a dynamic priority to IOU, D-cache and I-cache device requests as a function of intrinsic priority assigned to each device and a plurality of factors including the existence of a row match between a requested address and a previously serviced request, the number of times a device has been denied service and the number of times a device has been serviced without interruption;
• keeping track of the number of times each of said factors occurs;
• and
• changing the priority of said devices as a function of said intrinsic priority and said number.

A method of dynamically refreshing a memory in a multiprocessor architecture capable of supporting multiple processors comprising the steps of:

• generating a memory refresh request after a predetermined number of machine cycles in each of said processors;
• keeping track of the number of times said request is denied since the last time it was granted;
• and
• increasing the priority of said memory refresh request when said number reaches a predetermined magnitude such that said memory is refreshed within a predetermined time period by at least one of said processors.