Data transfer control device and electronic instrument

A data transfer control device for data transfer through a bus, comprising:

• a first conversion circuit which converts K-bit width data transferred in a high-speed first transfer mode through a bus into data having an L-bit width (L>K) by rearranging;
• a first processing circuit which receives the L-bit width data from the first conversion circuit and carries out a K-bit based process on an L-bit basis at a second frequency which is lower than a first frequency of the first transfer mode;
• a second processing circuit which processes on a K-bit basis a K-bit width data transferred in a low-speed second transfer mode through a bus;
• and
• a second conversion circuit which converts the K-bit width data from the second processing circuit into data having an L-bit width.

A data transfer control device for data transfer through a bus, comprising:

• a first conversion circuit which converts K-bit width data transferred in a high-speed first transfer mode through a bus into data having an L-bit width (L>K) by rearranging;
• a second conversion circuit which converts K-bit width data transferred in a low-speed second transfer mode through a bus into data having an L-bit width by rearranging;
• a selection circuit which selects and outputs one of an output from the first conversion circuit and an output from the second conversion circuit;
• and
• a processing circuit which receives the L-bit width data from the selection circuit and performs a K-bit based process on an L-bit basis at a second frequency which is lower than a first frequency of the first transfer mode.

A data transfer control device for data transfer through a bus, comprising:

• a first conversion circuit which converts K-bit width data transferred at a first frequency through a bus into data having an L-bit width (L>K) by rearranging;
• a processing circuit which receives the L-bit width data from the first conversion circuit and carries out an M-bit based process (L>M>K) on an L-bit basis at a second frequency which is lower than the first frequency;
• and
• a second conversion circuit which receives the L-bit width data from the processing circuit and converts the L-bit width data into data having an M-bit width by rearranging.

A data transfer control device for data transfer through a bus, comprising:

• a first processing circuit which receives data to be transferred on a K-bit basis in a high-speed first transfer mode through a bus as L-bit width data (L>K) and carries out a K-bit based process on an L-bit basis at a second frequency which is lower than a first frequency of the first transfer mode;
• and
• a first conversion circuit which converts the L-bit width data from the first processing circuit into data having a K-bit width by rearranging;
• a second conversion circuit which receives data to be transferred on the K-bit basis in a low-speed second transfer mode through a bus as L-bit width data and converts the L-bit width data into a K-bit width data by rearranging;
• and
• a second processing circuit which processes the K-bit width data from the second conversion circuit on the K-bit basis.

A data transfer control device for data transfer through a bus, comprising:

• a processing circuit which receives data to be transferred on a K-bit basis in a high-speed first transfer mode or a low-speed second transfer mode through a bus as L-bit width data (L>K) and carries out a K-bit based process on an L-bit basis at a second frequency lower than a first frequency of the first transfer mode;
• and
• a first conversion circuit which receives the L-bit width data to be transferred in the high-speed first transfer mode from the processing circuit and converts the L-bit width data into data having a K-bit width by rearranging;
• and
• a second conversion circuit for receives the L-bit width data to be transferred in the low-speed second transfer mode from the processing circuit and converts the L-bit width data into data having a K-bit width by rearranging.

A data transfer control device for data transfer through a bus, comprising:

• a first conversion circuit which receives data to be transferred on a K-bit basis at a first frequency through a bus as M-bit width data (M>K) and converts the M-bit width data into data having L-bit width (L>M>K) by rearranging;
• a processing circuit which receives the L-bit width data from the first conversion circuit and carries out an M-bit based process on an L-bit basis at a second frequency lower than the first frequency;
• and
• a second conversion circuit which converts the L-bit width data from the processing circuit into data having a K-bit width by rearranging.