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US 2002/0057712 A1Published application
Packet switching apparatus
AssigneeHitachi, Ltd.
InventorsNorihiko Moriwaki, Hidehiro Toyoda, Masayuki Takase
Life of this patent
Estimating the term…
Abstract
A packet switch has a switch section formed by a plurality of crossbar switch planes and plurality of interfaces, and each interface outputs in parallel input packets in block units to the plurality of crossbar switch planes in response to signals from a scheduler, wherein when n crossbar switch planes can be mounted on the packet switch, each interface allocates time slots corresponding to the n crossbar switch planes or when a switch plane is additionally mounted, a block is read at a time slot corresponding to the additional switch plane or when a switch plane is stopped from working, an idle time slot is used to prevent a block from being output to the switch plane which is unused.
Claims10
A packet switch comprising:
- a plurality of line interfaces each connectable to an input line and an output line;
- a back panel capable of mounting n crossbar switches each connected to said plurality of line interfaces, each of said plurality of line interfaces including input queue buffers as many as said plurality of line interfaces;
- a block distributor;
- and a read controller for reading input packets buffered in said plurality of input buffers, in fixed length block units at cyclic time slots allocated to said n crossbar switches, and sending read blocks to said distributor,
- wherein n crossbar switches are mounted on said back panel, said read controller reads n blocks from one input queue buffer selected out of said plurality of input buffers at time slots corresponding to said n crossbar switches, and sends said blocks to said block distributor, wherein said block distributor outputs said n blocks to said n crossbar switches, wherein when k crossbar switches out of said n crossbar switches are unused or faults occur in said k crossbar switches, said read controller reads n-k blocks from one selected input queue buffer out of said plurality of input queue buffers at time slots corresponding to n-k crossbar switches in operation and sends said blocks to said block distributor but does not read blocks at time slots corresponding to said k crossbar switches, and wherein said block distributor outputs said n-k blocks to said n-k crossbar switches in operation.
2 more elements
A packet switch comprising:
- a plurality of line interfaces each connectable to an input line and an output line;
- a back panel capable of mounting n crossbar switches each connected to said plurality of line interfaces, each of said plurality of line interfaces including input queue buffers as many as said plurality of line interfaces;
- a block distributor;
- and a read controller for reading input packets buffered in said plurality of input buffers, in fixed length block units at cyclic time slots allocated to said n crossbar switches, and sending read blocks to said block distributor,
- wherein when n-k crossbar switches are mounted on said back panel, said read controller reads n-k blocks from one input queue buffer selected out of said plurality of input buffers at time slots allocated to said n-k crossbar switches, and sends said blocks to said block distributor, but does not read blocks at time slots allocated to k crossbar switches not mounted on said back panel, wherein said block distribution controller outputs said n-k blocks to said n-k crossbar switches, wherein when one crossbar switch is additionally mounted to said back panel, said read controller reads n-k+l blocks from one input queue buffer selected out of said plurality of input queue buffers at time slots allocated to said n-k crossbar switches and also at time slots corresponding to said additionally mounted crossbar switch, sends said blocks to said block distributor, and said block distributor outputs said n-k+1 blocks to said n-k crossbar switches and said additionally mounted crossbar switch.
2 more elements
A packet switch comprising:
- a plurality of line interfaces each connectable to an input line and an output line;
- a back panel capable of mounting n crossbar switches each connected to said plurality of line interfaces, each of said plurality of line interfaces including input queue buffers as many as said plurality of line interfaces;
- a block distributor;
- and a read controller for reading input packets buffered in said plurality of input buffers, in fixed length block units at cyclic time slots allocated to said n crossbar switches, and sending read blocks to said distributor,
- wherein n crossbar switches are in operation on said back panel, said read controller reads n blocks from one input queue buffer selected out of said plurality of input buffers at time slots corresponding to said n crossbar switches, and sends said blocks to said block distributor, wherein said block distributor outputs each of said n blocks to a crossbar switch corresponding to a time slot at which the block was read, wherein when k crossbar switches out of said n crossbar switches are unused or faults occur in said k crossbar switches, said read controller reads n-k blocks from one selected input queue buffer out of said plurality of input queue buffers at time slots corresponding to n-k crossbar switches in operation and sends said blocks to said block distributor but does not read blocks at time slots corresponding to said k crossbar switches, and wherein said block distributor outputs said n-k blocks to crossbar switches corresponding to time slots at which said blocks were read.
2 more elements
Dependencies are inferred from the claim text.