Message writing apparatus, message writing method, message readout apparatus, message readout method, memory address control circuit for writing of variable-length message and memory address control circuit for readout of variable-length message

A message writing method characterized by comprising:

• a receiving step of receiving cells having path information, said cells being obtained by division of a variable-length message;
• a message area allocating step of extracting said path information from the received cells received in said receiving step to allocate a memory area (22) corresponding to said path information, said memory area (22) being larger than a size of said variable-length message;
• a writing rank adding step of adding writing ranks to the received cells when the received cells are written in said memory area (22) allocated in said message area allocating step;
• and
• a storing step of writing the received cells in said memory area (22) according to said writing ranks added in said writing rank step.

A message readout apparatus (20) which reads out each of a plurality of cells constituting a message and written in a memory area (22), characterized by comprising:

• first means (22, 25) for reading out said message in accordance with writing ranks added in the order of receive processing of said cells;
• second means (22, 25) for reading out said message on the basis of the added writing ranks in a manner that flag information, indicative of whether or not said cells are read out, is written in said memory area (22);
• third means (22, 25) for reading out said message on the basis of said writing ranks based on an indication of a message storing/holding section (41a, 41b, 41c) which manages a message number of the received cells written in said memory area and writing position information thereon;
• and
• control means (23) operable of selecting any one of said first means (22, 25), said second means (22, 25) and said third means (22, 25) by setting of said memory area (22).

A message readout method of reading out each of a plurality of cells constituting a message and written in a memory area (22), characterized by comprising:

• a first step of reading out said message in accordance with writing ranks added in the order of receive processing of said cells;
• a second step of reading out said message on the basis of the added writing ranks in a manner that flag information, indicative of whether or not the cells are read out, is written in said memory area (22);
• and
• a third step of reading out said message in accordance with said writing ranks provided by an indication of a message storing/holding section (41a, 41b, 41c) which manages a message number of the received cells written in said memory area (22) and writing position information,
• with any one of said first means, said second means and said third means being selectively implemented according to setting of said memory area (22).

A memory address control circuit for writing of a variable-length message, characterized by comprising:

• a path recognizing section (21a) for receiving cells, said cells being obtained by division said variable-length message and transmitted to extract path information from the received cells;
• a receive control section (21c) operable of adding writing ranks on writing in a memory (22) in correspondence with said path information outputted from said path recognizing section (21a) and of outputting a size of a writing area, a writing position of said variable-length message and the number of received cells as management information;
• a received message assembling section (21b) having an address table (23), in which said size of said writing area, said writing position of said variable-length message and the number of received cells, corresponding to said path information, are related to each other on the basis of said management information from said receive control section and operable of assembling the received cells with respect to one variable-length message and outputting second write information:
• and
• a memory control section (21e) operable of controlling writing in said memory (22) on the basis of said management information from said received message assembling section (21b) and the second write information from the receive control section (21c).

A memory address control circuit for readout of a variable-length message, characterized by comprising:

• a path recognizing section (21a) for receiving cells, said cells being obtained by division of said variable-length message and transmitted to extract path information from the received cells;
• a receive control section (21c) operable of adding writing ranks on readout from a memory (22) in correspondence with said path information outputted from said path recognizing section (21a) and of outputting a size of a readout area, a readout position of said variable-length message and the number of received cells as management information;
• a received message assembling section (21b) having an address table (23), in which said size of said readout area, said readout position of said variable-length message and the number of received cells being corresponding to said path information, are related to each other on the basis of said management information from said receive control section (21c) and operable of assembling the received cells with respect to one variable-length message to output and outputting second readout information;
• and
• a memory control section (21e) operable of controlling the readout to said memory (22) on the basis of said management information from said received message assembling section (21b) and said second readout information from said receive control section.