Reading circuit for semiconductor non-volatile memories

A reading circuit for non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit comprising:

• first and second current/voltage conversion circuits receiving at their respective inputs thereof a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on their outputs on a first circuit node a selected cell voltage and on a node a second reference cell voltage;
• at least one differential amplifier having inputs connected to the first and second nodes and having an output terminal configured to supply a logic signal correlating to the information contained in the selected cell;
• at least one first voltage-controlled discharge switch circuit connected to the input of the first circuit node and to a voltage reference, a second voltage-controlled discharge switch circuit connected to the input of the second node and to the voltage reference, and at least a first and a second voltage comparator circuit receiving at their respective inputs thereof the selected cell voltage and the reference cell voltage, the comparator circuits comprising differential comparators of the module of the difference between the selected cell voltage and the reference cell voltage with respect to a value corresponding to a tripping voltage for the startup of the discharge switch circuits, the value corresponding to a tripping voltage that comprises a fixed voltage reference.

A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit comprising:

• first and second conversion circuits coupled to receive a first current from the selected cell and as second current from the reference cell, respectively, and configured to generate a first voltage and a second voltage in response thereto;
• a differential amplifier having first and second inputs coupled to receive the first and second voltages at first and second nodes, respectively, and to generate a logic signal at an output thereof that is correlated to a state of the selected cell;
• a first switching circuit and a second switching circuit coupled to the first and second nodes, respectively, each switching circuit further coupled to a voltage reference terminal, the first and second switching circuits configured to selectively couple and uncouple the respective first and second nodes to the voltage reference terminal in response to a control signal;
• and
• first and second comparator circuits configured to receive the first and second voltages and to send the control signal to each of the first and second switching circuits to couple the respective node to the voltage reference terminal when the magnitude of the difference between the first and second voltages is equal to or greater than a tripping voltage value.

A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit comprising:

• first and second conversion circuits coupled to receive a first current from the selected cell and a second current from the reference cell, respectively, and configured to generate a first voltage and a second voltage in response thereto;
• a differential amplifier having first and second inputs coupled to receive the first and second voltages at first and second nodes, respectively, and to generate a logic signal correlated to a state of the selected cell;
• and
• a first and second discharge circuit coupled between the first and second nodes, respectively, and a voltage reference, and configured to couple the respective node to the voltage reference when the magnitude of the difference between the first and second voltages is equal to or greater than a predetermined voltage value.

A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit comprising:

• first and second conversion circuits coupled to receive a first current from the selected cell and a second current from the reference cell, respectively, and configured to generate a first voltage and a second voltage in response thereto;
• a differential amplifier having first and second inputs coupled to receive the first and second voltages at first and second nodes, respectively, and to generate a logic signal correlated to a state of the selected cell;
• and
• a first and second discharge circuit coupled between the first and second nodes, respectively, and a voltage reference, the first and second discharge circuits configured to receive the first and second voltages, the first and second discharge circuits configured such that the first and second node having the slowest variation in voltage is coupled to the voltage reference when the magnitude of the difference between the first and second voltages is equal to or greater than a fixed reference voltage.