Circuit for generating timing of reference plate line in nonvolatile ferroelectric memory device and method for driving reference cell

Abstract

In a circuit for generating timing of a reference plate line in the nonvolatile ferroelectric memory device, wherein a nonvolatile ferroelectric memory device having a reference cell includes a switching block controlled by a reference wordline signal, a level initiating block which selectively initiates a level of an input terminal of the switching block after receiving a reference equalizer signal, and a plurality of ferroelectric capacitors connected in parallel between the input terminal of the switching block and the reference plate line, the circuit includes a latch circuit receiving a first signal which has the same waveform as that of a chip enable signal and is not delayed and a second signal which has the same waveform as that of the chip enable signal and is delayed for a first period as the chip enable signal is generated, so as to output a low signal only in a delayed period of the second signal, and a delay circuit delaying the first and second signals of the latch circuit to output a low signal to the reference plate line.

Dependencies are inferred from the claim text.