Method for driving nonvolatile ferroelectric memory device

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of sub cell arrays comprising a plurality of main cells and one or more reference cells, among which a reference cell of one of the sub cell arrays operates with a main cell of an adjacent sub cell array, each of the main cells and the reference cells including at least one transistor and one or more ferroelectric capacitors coupled to a bitline, each main cell including a main cell wordline and a plate line, and each reference cell including a reference wordline and a reference plate line, the method comprising the steps of:

• primarily activating one of the a main cell wordlines of a sub cell array, an adjacent reference wordline of an adjacent cell array, the corresponding plate line of the main cell, and the reference plate line of the corresponding reference cell to a high level;
• deactivating the wordline and the reference wordline;
• precharging a chip enable signal by transiting the chip enable signal to high level;
• activating a sensing amplifier after the wordline is inactivated;
• secondarily activating the wordline to high level during the precharge period in a state that the sensing amplifier is activated;
• and
• activating the plate line to coincide with an initial portion of the period when the main cell wordline is secondarily activated to the high level.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of sub cell arrays, each sub cell array comprising a plurality of main cells and one or more reference cells, among which a reference cell of one of the sub cell arrays operates with a main cell of an adjacent sub cell array, each main cell and each reference cell including at least one transistor and one or more ferroelectric capacitors coupled to a bitline, each main cell further including a main cell wordline and a plate line, and each reference cell including a reference wordline and a reference plate line, the method comprising the steps of:

• primarily activating a main cell wordline of one of the sub cell arrays, a reference wordline of a sub cell array adjacent to the cell array including the activated main cell wordline, the plate line the one of the sub cell arrays, and the reference plate line of the adjacent reference cell to high level;
• deactivating the wordline and the reference wordline;
• activating a sensing amplifier after the wordline is inactivated;
• deactivating the plate line and the reference plate line;
• secondarily activating the main cell wordline to a high level;
• precharging a chip enable signal by transiting the chip enable signal to high level;
• and
• secondarily activating the plate line to coincide with an initial portion of period during which the main cell wordline is secondarily activated.

A method for driving a nonvolatile ferroelectric memory device that includes a plurality of sub cell arrays, each sub cell array comprising a plurality of main cells and one or more reference cells, among which a reference cell of one of the sub cell arrays operates with a main cell of an adjacent sub cell array, each main cell and each reference cell including at least one transistor and one or more ferroelectric capacitors coupled to a bitline, each main cell further including a main cell wordline and a plate line, and each reference cell including a reference wordline and a reference plate line, the method comprising the steps of:

• primarily activating a main cell wordline of one of the sub cell arrays, a reference wordline of a sub cell array adjacent to the cell array including the activated main cell wordline, the plate line the one of the sub cell arrays, and the reference plate line of the adjacent reference cell to high level;
• deactivating the main cell wordline and the reference wordline;
• activating a sensing amplifier after the wordline is inactivated;
• deactivating the plate line and the reference plate line;
• precharging a chip enable signal by transiting the chip enable signal to high level;
• and
• secondarily activating the plate line to coincide with a latter portion of the period during which the main cell wordline is secondarily activated.