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US 2002/0057092 A1Published application
Device and method for checking integrated capacitors
AssigneeSTMicroelectronics S.r.l.
InventorsRaul Andres Bianchi, Benoit Froment
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AssigneeSTMicroelectronics S.r.l.
InventorsRaul Andres Bianchi, Benoit Froment
Estimating the term…
A device includes a capacitive structure including an input node and n output nodes, r integrated capacitors connected in series between two adjacent nodes, an integrated capacitor connected between the input node and ground, an integrated capacitor connected between the nth output node and ground, and r capacitive branches connected in parallel between ground and each node of the capacitive structure including the first output node and the (n−1)th output node. Each branch may include r+1 series-connected integrated capacitors. Furthermore, the integrated capacitors of the capacitive structure are theoretically identical. The device may also include a charge source for charging each node of the capacitive structure. Additionally, a measurement circuit may measure the charge at each of the nodes of the structure, and a comparison circuit may compare each measured nodal charge value with a theoretical nodal charge value while taking into account a predetermined nodal tolerance.
Device for checking theoretically identical integrated capacitors, comprising:
Device according to one of the preceding claims, characterized in that the measurement means comprise, for each node of the capacitive structure, a controllable measurement switch (Si) connected to the said node and an ammeter (Amp) capable of being connected between the measurement switch and earth.
Device according to one of the preceding claims, characterized in that it comprises, for each node of the capacitive structure, a controllable discharge switch (Sres) connected between the said node and earth.
Device according to one of the preceding claims, used for checking integrated capacitors belonging to an integrated circuit (IC) located on a die (DIE) of a semiconductor wafer (SCW) and bounded by dicing streets (DS) made in the said wafer, characterized in that the capacitive structure (CAS) is inserted into one of the dicing streets by which the said die is bounded, the plate surface area of the capacitors (C) of the capacitive structure being at most equal to the minimum plate surface area of the capacitors of the integrated circuit.
Method for checking theoretically identical integrated capacitors, in which:
Dependencies are inferred from the claim text.