Circuit for reducing test time and semiconductor memory device including the circuit

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells, a plurality of word lines, and a plurality of bit lines;
• a read circuit reading out data from said memory cell array;
• and
• a test facilitating circuit including a non-coincidence holding circuit receiving a determination result showing coincidence/non-coincidence between said read data and an expected value and a control signal at an input thereof,
• wherein when said control signal shows a transmission state, said non-coincidence holding circuit catches said determination result, while when said control signal shows an accumulation state different from said transmission state, once said non-coincidence holding circuit catches said determination result showing said non-coincidence, thereafter said non-coincidence holding circuit holds said determination result showing said non-coincidence till said control signal shows said transmission state.