Electronic control apparatus with memory validation and method
AssigneeMotorola, Inc.
InventorsROSS BANNATYNE, CLAY E. MERRITT, NANCY L. THOMAS
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Abstract
A method and apparatus for confirming the operation of memory (212) operates during periods when the memory is not operating in a standard execution mode. This strategy allows the memory to be checked real-time without impacting normal bandwidth of an associated CPU (200). The method and apparatus guarantees deterministic testing by including circuitry and steps which force bus mastership and, therefore, memory access if the memory is busy for too long a period of time.
Claims30
A memory validation system comprising:
- signature generation logic responsive to data retrievable from a bus coupled to a memory during a second access period when the bus is free, where the bus is controllable by a device operating in a standard execution mode during a first access period, the first access period occurring before the second access period, the signature generation logic having an output that produces a first data item that correlates to the data retrieved from the bus;
- and
- a comparator responsive to the output of the signature generation logic to compare the first data item to a predetermined second data item.
An apparatus comprising:
- a memory;
- a bus coupled to the memory;
- a device coupled to the bus to control the bus during a first time period;
- a memory validation system including:
- signature generation logic responsive to data retrievable from the bus during a second time period when the bus is free from control of the device, the signature generation logic having an output to produce a first data item;
- and
- a comparator responsive to the output of the signature generation logic to compare the first data item to a predetermined second data item.
An electronic control apparatus comprising:
- an input interface to receive signals from at least one sensor;
- a digital controller responsive to the input interface, the digital controller including:
- a memory;
- a bus coupled to the memory;
- a device coupled to the bus to control the bus during a first time period;
- a memory validation system including:
- signature generation logic responsive to data retrievable from the bus during a second time period when the bus is free from control of the device, the signature generation logic having an output to produce a first data item;
- and
- a comparator responsive to the output of the signature generation logic to compare the first data item to a predetermined second data item;
- and an output interface responsive to the digital controller.
A method of processing data to validate memory content, the method comprising:
- determining whether a bus coupled to a memory is available for access;
- fetching data from the bus when the bus is available for access;
- performing signature generation on the data to produce a first data item;
- and
- comparing the first data item with a second data item.
Dependencies are inferred from the claim text.