Instruction sets for processors

Processor instruction encodings having:

• respective first and second external instruction formats in which the instructions are received by a processor, each instruction having an opcode which specifies an operation to be executed, and each external format having one or more preselected opcode bits in which the opcode appears;
• an internal instruction format into which the processor instructions in the external formats are translated prior to execution of the operations;
• wherein:
• a first operation executable by the processor is specifiable in both said first and second external formats, and a second operation executable by the processor is specifiable in said second external format;
• said first and second operations have distinct opcodes in said second external format;
• and
• in each said preselected opcode bit which the first and second external formats have in common, the opcodes of the first operation in the two external formats are identical.

A method of encoding instructions for a processor having two or more external instruction formats and one or more internal instruction formats, the method comprising:

• (a) selecting initial encoding parameters including a number of effective opcode bits in each external and internal format and a set of mapping functions, each said mapping function serving to translate an opcode specified by said opcode bits in one of the external formats to an opcode specified by said opcode bits in the, or in one of the, internal formats;
• (b) allocating each operation executable by the processor an opcode distinct from that allocated to each other operation in each external and internal format in which the operation is specifiable, the allocated opcodes being such that each relevant mapping function translates such an external-format opcode allocated to the operation into such an internal-format opcode allocated to the operation and such that all the internal-format opcodes allocated to the operation have the same effective opcode bits;
• and
• (c) if in the allocation (b) no opcode is available for allocation in each specifiable format for every one of said operations, determining which of said encoding parameters is constraining the allocation (b), relaxing the constraining parameter, and then repeating the allocation (b).

A computer-readable recording medium storing a program which, when executed, encodes instructions for a processor having two or more external instruction formats and one or more internal instruction formats, said program comprising:

• (a) a selecting code portion which selects initial encoding parameters including a number of effective opcode bits in each external and internal format and a set of mapping functions, each said mapping function serving to translate an opcode specified by said opcode bits in one of the external formats to an opcode specified by said opcode bits in the, or in one of the, internal formats;
• (b) an allocating code portion which allocates each operation executable by the processor an opcode distinct from that allocated to each other operation in each external and internal format in which the operation is specifiable, the allocated opcodes being such that each relevant mapping function translates such an external-format opcode allocated to the operation into such an internal-format opcode allocated to the operation and such that all the internal-format opcodes allocated to the operation have the same effective opcode bits;
• and
• (c) a determining code portion which, if no opcode is available to the allocating code portion for allocation in each specifiable format for every one of said operations, determines which of said encoding parameters is constraining the allocation in step (b), and relaxes the constraining parameter, and then causes the allocating code portion to repeat the allocation of opcodes.