Pipelined multi-access memory apparatus and method

A memory management system, comprising:

• a memory divided into a plurality of memory blocks;
• and
• a plurality of memory block management circuits, each of the plurality of memory blocks associated with one of the memory block management circuits, wherein each memory block management circuit is configured to:
• receive one or more requests from one or more requesters for one or more of the plurality of memory blocks, and
• on a single clock cycle,
• determine whether one of the memory blocks is requested by one or more of the requesters,
• determine which request is provided to said one of the memory blocks if one of the memory blocks is requested by one or more of the requesters, and
• provide the determined request to said one of the memory blocks.

A method of processing requests for memory, comprising:

• during a first clock,
• driving a first set of one or more requests from one or more requesters onto a request bus,
• performing a first determination whether one of a plurality of memory blocks is requested by the one or more requests, and
• if two or more requesters issue requests for one of the plurality of memory blocks,
• performing a second determination of which request of the two or more requests is provided to said one of the memory blocks.

A method of writing pipelined data to a single port memory, comprising:

• during a first clock,
• receiving a set of requests for one or more of the memory blocks,
• determining whether one of the memory blocks is requested by one or more requests, and
• determining which request is provided to said one of the memory blocks;
• and
• during a second clock,
• latching data of the determined request to said one of the memory blocks,
• accessing said one of the memory blocks, and
• writing data of the determined request to said one of the memory blocks.

A method of reading pipelined data from a single port memory, comprising

• during a first clock,
• receiving a plurality of requests for one or more of the memory blocks,
• determining whether one of the memory blocks is requested by one or more requests of the plurality of requests, and
• if one or more of the memory blocks is requested by one or more requests, determining which request is provided to said one of the memory blocks;
• during a second clock,
• latching data of the determined request to said one of the memory blocks,
• accessing said one of the memory blocks, and
• retrieving requested data from said one of the memory blocks;
• and
• during a third clock,
• driving the retrieved data from said one of the memory blocks requested data onto a return bus,
• routing the retrieved data to the determined requester, and
• during a fourth clock,
• latching the retrieved data to the determined requester.

A system for writing pipelined data to a single port memory, comprising:

• during a first clock,
• means for receiving a set of requests for one or more of the memory blocks,
• means for determining whether one of the memory blocks is requested by one or more requests, and
• if one or more of the memory blocks is requested by one or more requests, means for determining which request is provided to said one of the memory blocks;
• and
• during a second clock,
• means for latching data of the determined request to said one of the memory blocks,
• means for accessing said one of the memory blocks, and
• means for writing data of the determined request to said one of the memory blocks.

A system for reading pipelined data from a single port memory, comprising:

• during a first clock,
• means for receiving a plurality of requests for one or more of the memory blocks,
• means for determining whether one of the memory blocks is requested by one or more requests of the plurality of requests, and
• if one or more of the memory blocks is requested by one or more requests, means for determining which request is provided to said one of the memory blocks;
• during a second clock,
• means for latching data of the determined request to said one of the memory blocks,
• means for accessing said one of the memory blocks, and
• means for retrieving requested data from said one of the memory blocks;
• and
• during a third clock,
• means for driving the retrieved data from said one of the memory blocks requested data onto a return bus,
• means for routing the retrieved data to a memory corresponding to the determined requester, and
• during a fourth clock,
• means for latching the retrieved data to the determined requester.