US 2002/0056028 A1Published application

Method and system for controlling the memory access operation by central processing unit in a computer system

AssigneeVIA Technologies, Inc.

InventorNai-Shung Chang

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Abstract

A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner. This memory access control method and system is characterized in the capability of switching the memory access operation between a waiting mode and a non-waiting mode based on the current L1write-back condition of the read requests from the CPU. In the waiting mode, the memory unit responds to each read request in such a manner as to wait until the L1write-back signal of the read request is issued and then either perform a read operation for the current read request if the L1write-back signal indicates a cache miss, or perform a cache write-back operation if the L1write-back signal indicates a cache hit. In the non-waiting mode, the memory unit responds to each read request in such a manner that it will always promptly perform a read operation for the current read request without waiting until the CPU issues the L1write-back signal of the current read request, and in the event that the subsequently received L1write-back signal of the read request indicates a cache hit, promptly abandon the currently retrieved data from the memory unit and then performing a cache write-back operation.

Claims7

Dependent claims

A memory access control system for controlling the memory access operation by a CPU to a memory unit, the CPU being capable of issuing a series of read requests each time the CPU intends to read data from the memory unit and being further capable of issuing an L1write-back signal indicative whether the current read request is a hit or a miss to the cache memory after a first delayed period after the current read request is issued, and in the event that the L1write-back signal of the current read request indicates a cache hit, issuing a cache write-back request to perform a cache write-back operation to write the output cache data from the CPU back into the memory unit after a second delayed period after the L1write-back signal is issued;

the memory access control system comprising:
(a) a CPU interface coupled to the CPU, which is capable of being selectively switched to operate between a waiting mode and a non-waiting mode;
in the waiting mode, the CPU interface responding to each read request from the CPU in such a manner as to wait until the L1write-back signal of the current read request is received and then issue a corresponding internal read-request signal if the L1write-back signal indicates a cache miss, or a corresponding internal cache write-back request signal if the L1write-back signal indicates a cache hit;
and in the non-waiting mode, the CPU interface responding to each read request from the CPU in such a manner that the CPU interface will promptly issue the corresponding internal read-request signal without waiting until the CPU issues the L1write-back signal of the current read request, and in the event that the subsequently issued L1write-back signal of the current read request indicates a cache hit, promptly issue a read-stop signal for the current read request;
(b) a memory control unit coupled between the CPU interface and the memory unit, which is capable of performing a read operation on the memory unit in response to each internal read-request signal from the CPU interface, and further in response to the read-stop signal, is capable of abandoning the currently retrieved data from the memory unit demanded by the current read request and then performing a cache write-back operation to write back the subsequent output cache data from the CPU back into the memory unit;
and
(c) a mode-switching unit coupled between the CPU interface and the CPU, which is initially set to switch the CPU interface to operate in the waiting mode, and is further capable of detecting whether each read request from the CPU is a cache hit or a cache miss and counting the number of consecutive cache-miss read requests to thereby switch the CPU interface to the non-waiting mode when the count reaches a preset threshold.

4 more elements

A memory access control method for controlling the memory access operation by a CPU to a memory unit, the CPU being capable of issuing a series of read requests each time the CPU intends to read data from the memory unit and being further capable of issuing an L1write-back signal indicative whether the current read request is a hit or a miss to the cache memory after a first delayed period after the current read request is issued, and in the event that the L1write-back signal of the current read request indicates a cache hit, issuing a cache write-back request to perform a cache write-back operation to write the output cache data back from the CPU into the memory unit after a second delayed period after the L1write-back signal is issued;

the memory access control method comprising:
(1) performing a mode-switching process to switch the memory access operation between a waiting mode and a non-waiting mode;
the memory access operation being switched to the waiting mode during the time when the currently issued read requests are each a cache hit, and to the waiting mode when the currently issued read request are each a cache miss;
(2) in the waiting mode, responding to each read request from the CPU until the CPU issues the L1write-back signal of the current read request;
and
(3) in the non-waiting mode, promptly responding to each read request from the CPU without waiting until the CPU issues the L1write-back signal of the current read request.

3 more elements

Dependencies are inferred from the claim text.